Commit ce689628 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'samsung-clk-6.10-2' of... 

Merge tag 'samsung-clk-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung clk driver updates from Krzysztof Kozlowski:

 - Allow choice of manual or firmware-driven control over PLLs, needed
   to fully implement CPU clock controllers on Exynos850
 - Correct PLL clock IDs on ExynosAutov9
 - Propagate certain clock rates to allow setting proper SPI clock
   rates on Google GS101
 - Add HSI0 and HSI2 clock controllers for Google GS101
 - Mark certain Google GS101 clocks critical
 - Convert old S3C64xx clock controller bindings to DT schema

* tag 'samsung-clk-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: gs101: drop unused HSI2 clock parent data
  clk: samsung: gs101: mark some apm UASC and XIU clocks critical
  clk: samsung: gs101: add support for cmu_hsi2
  clk: samsung: gs101: add support for cmu_hsi0
  dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit
  dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit
  clk: samsung: gs101: propagate PERIC1 USI SPI clock rate
  clk: samsung: gs101: propagate PERIC0 USI SPI clock rate
  clk: samsung: exynosautov9: fix wrong pll clock id value
  dt-bindings: clock: samsung,s3c6400-clock: convert to DT Schema
  clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1
  clk: samsung: Implement manual PLL control for ARM64 SoCs
parents 4cece764 7c18b0a5

Documentation/devicetree/bindings/clock/google,gs101-clock.yaml

+53 −2
Original line number Diff line number Diff line
@@ -30,16 +30,18 @@ properties: 
      - google,gs101-cmu-top

      - google,gs101-cmu-apm

      - google,gs101-cmu-misc

      - google,gs101-cmu-hsi0

      - google,gs101-cmu-hsi2

      - google,gs101-cmu-peric0

      - google,gs101-cmu-peric1



  clocks:

    minItems: 1

    maxItems: 3

    maxItems: 5



  clock-names:

    minItems: 1

    maxItems: 3

    maxItems: 5



  "#clock-cells":

    const: 1
@@ -72,6 +74,55 @@ allOf: 
          items:

            - const: oscclk



  - if:

      properties:

        compatible:

          contains:

            const: google,gs101-cmu-hsi0



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (24.576 MHz)

            - description: HSI0 bus clock (from CMU_TOP)

            - description: DPGTC (from CMU_TOP)

            - description: USB DRD controller clock (from CMU_TOP)

            - description: USB Display Port debug clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: bus

            - const: dpgtc

            - const: usb31drd

            - const: usbdpdbg



  - if:

      properties:

        compatible:

          contains:

            enum:

              - google,gs101-cmu-hsi2



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (24.576 MHz)

            - description: High Speed Interface bus clock (from CMU_TOP)

            - description: High Speed Interface pcie clock (from CMU_TOP)

            - description: High Speed Interface ufs clock (from CMU_TOP)

            - description: High Speed Interface mmc clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: bus

            - const: pcie

            - const: ufs

            - const: mmc



  - if:

      properties:

        compatible:

Documentation/devicetree/bindings/clock/samsung,s3c6400-clock.yaml

0 → 100644
+57 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/samsung,s3c6400-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Samsung S3C6400 SoC clock controller



maintainers:

  - Krzysztof Kozlowski <krzk@kernel.org>



description: |

  There are several clocks that are generated outside the SoC. It is expected

  that they are defined using standard clock bindings with following

  clock-output-names and/or provided as clock inputs to this clock controller:

   - "fin_pll" - PLL input clock (xtal/extclk) - required,

   - "xusbxti" - USB xtal - required,

   - "iiscdclk0" - I2S0 codec clock - optional,

   - "iiscdclk1" - I2S1 codec clock - optional,

   - "iiscdclk2" - I2S2 codec clock - optional,

   - "pcmcdclk0" - PCM0 codec clock - optional,

   - "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.



  All available clocks are defined as preprocessor macros in

  include/dt-bindings/clock/samsung,s3c64xx-clock.h header.



properties:

  compatible:

    enum:

      - samsung,s3c6400-clock

      - samsung,s3c6410-clock



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    clock-controller@7e00f000 {

        compatible = "samsung,s3c6410-clock";

        reg = <0x7e00f000 0x1000>;

        #clock-cells = <1>;

        clocks = <&fin_pll>;

    };

Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt

deleted100644 → 0
+0 −76
Original line number Diff line number Diff line 
* Samsung S3C64xx Clock Controller



The S3C64xx clock controller generates and supplies clock to various controllers

within the SoC. The clock binding described here is applicable to all SoCs in

the S3C64xx family.



Required Properties:



- compatible: should be one of the following.

  - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.

  - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.



- reg: physical base address of the controller and length of memory mapped

  region.



- #clock-cells: should be 1.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. Some of the clocks are available only

on a particular S3C64xx SoC and this is specified where applicable.



All available clocks are defined as preprocessor macros in

dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device

tree sources.



External clocks:



There are several clocks that are generated outside the SoC. It is expected

that they are defined using standard clock bindings with following

clock-output-names:

 - "fin_pll" - PLL input clock (xtal/extclk) - required,

 - "xusbxti" - USB xtal - required,

 - "iiscdclk0" - I2S0 codec clock - optional,

 - "iiscdclk1" - I2S1 codec clock - optional,

 - "iiscdclk2" - I2S2 codec clock - optional,

 - "pcmcdclk0" - PCM0 codec clock - optional,

 - "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.



Example: Clock controller node:



	clock: clock-controller@7e00f000 {

		compatible = "samsung,s3c6410-clock";

		reg = <0x7e00f000 0x1000>;

		#clock-cells = <1>;

	};



Example: Required external clocks:



	fin_pll: clock-fin-pll {

		compatible = "fixed-clock";

		clock-output-names = "fin_pll";

		clock-frequency = <12000000>;

		#clock-cells = <0>;

	};



	xusbxti: clock-xusbxti {

		compatible = "fixed-clock";

		clock-output-names = "xusbxti";

		clock-frequency = <48000000>;

		#clock-cells = <0>;

	};



Example: UART controller node that consumes the clock generated by the clock

  controller (refer to the standard clock bindings for information about

  "clocks" and "clock-names" properties):



		uart0: serial@7f005000 {

			compatible = "samsung,s3c6400-uart";

			reg = <0x7f005000 0x100>;

			interrupt-parent = <&vic1>;

			interrupts = <5>;

			clock-names = "uart", "clk_uart_baud2",

					"clk_uart_baud3";

			clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,

					<&clock SCLK_UART>;

		};

drivers/clk/samsung/clk-exynos-arm64.c

+41 −15
Original line number Diff line number Diff line
@@ -17,10 +17,17 @@ 


#include "clk-exynos-arm64.h"



/* PLL register bits */

#define PLL_CON1_MANUAL		BIT(1)



/* Gate register bits */

#define GATE_MANUAL		BIT(20)

#define GATE_ENABLE_HWACG	BIT(28)



/* PLL_CONx_PLL register offsets range */

#define PLL_CON_OFF_START	0x100

#define PLL_CON_OFF_END		0x600



/* Gate register offsets range */

#define GATE_OFF_START		0x2000

#define GATE_OFF_END		0x2fff
@@ -38,17 +45,36 @@ struct exynos_arm64_cmu_data { 
	struct samsung_clk_provider *ctx;

};



/* Check if the register offset is a GATE register */

static bool is_gate_reg(unsigned long off)

{

	return off >= GATE_OFF_START && off <= GATE_OFF_END;

}



/* Check if the register offset is a PLL_CONx register */

static bool is_pll_conx_reg(unsigned long off)

{

	return off >= PLL_CON_OFF_START && off <= PLL_CON_OFF_END;

}



/* Check if the register offset is a PLL_CON1 register */

static bool is_pll_con1_reg(unsigned long off)

{

	return is_pll_conx_reg(off) && (off & 0xf) == 0x4 && !(off & 0x10);

}



/**

 * exynos_arm64_init_clocks - Set clocks initial configuration

 * @np:		CMU device tree node with "reg" property (CMU addr)

 * @reg_offs:		Register offsets array for clocks to init

 * @reg_offs_len:	Number of register offsets in reg_offs array

 * @cmu:	CMU data

 *

 * Set manual control mode for all gate clocks.

 * Set manual control mode for all gate and PLL clocks.

 */

static void __init exynos_arm64_init_clocks(struct device_node *np,

		const unsigned long *reg_offs, size_t reg_offs_len)

					    const struct samsung_cmu_info *cmu)

{

	const unsigned long *reg_offs = cmu->clk_regs;

	size_t reg_offs_len = cmu->nr_clk_regs;

	void __iomem *reg_base;

	size_t i;
@@ -60,15 +86,15 @@ static void __init exynos_arm64_init_clocks(struct device_node *np, 
		void __iomem *reg = reg_base + reg_offs[i];

		u32 val;



		/* Modify only gate clock registers */

		if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)

			continue;



		if (cmu->manual_plls && is_pll_con1_reg(reg_offs[i])) {

			writel(PLL_CON1_MANUAL, reg);

		} else if (is_gate_reg(reg_offs[i])) {

			val = readl(reg);

			val |= GATE_MANUAL;

			val &= ~GATE_ENABLE_HWACG;

			writel(val, reg);

		}

	}



	iounmap(reg_base);

}
@@ -177,7 +203,7 @@ void __init exynos_arm64_register_cmu(struct device *dev, 
		pr_err("%s: could not enable bus clock %s; err = %d\n",

		       __func__, cmu->clk_name, err);



	exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);

	exynos_arm64_init_clocks(np, cmu);

	samsung_cmu_register_one(np, cmu);

}
@@ -224,7 +250,7 @@ int __init exynos_arm64_register_cmu_pm(struct platform_device *pdev, 
		       __func__, cmu->clk_name, ret);



	if (set_manual)

		exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);

		exynos_arm64_init_clocks(np, cmu);



	reg_base = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(reg_base))

drivers/clk/samsung/clk-exynos850.c

+439 −1

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