Commit ce74bece authored by Ilya Bakoulin's avatar Ilya Bakoulin Committed by Alex Deucher
Browse files

drm/amd/display: Fix DP2.0 timing sync 



[Why]
Triggering OTG sync before all OTG/HPO clock programming is complete
causes timing sync to fail and a subsequent P-state hang.

[How]
Move DTB clock programming earlier in the sequence to
enable_stream_timing.

Reviewed-by: default avatarAriel Bernstein <eric.bernstein@amd.com>
Acked-by: default avatarWayne Lin <wayne.lin@amd.com>
Signed-off-by: default avatarIlya Bakoulin <ilya.bakoulin@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1288d702

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+48 −31
Original line number Diff line number Diff line
@@ -670,6 +670,37 @@ static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 
	return flow_ctrl_cnt;

}



static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)

{

	switch (link->link_enc->transmitter) {

	case TRANSMITTER_UNIPHY_A:

		return PHYD32CLKA;

	case TRANSMITTER_UNIPHY_B:

		return PHYD32CLKB;

	case TRANSMITTER_UNIPHY_C:

		return PHYD32CLKC;

	case TRANSMITTER_UNIPHY_D:

		return PHYD32CLKD;

	case TRANSMITTER_UNIPHY_E:

		return PHYD32CLKE;

	default:

		return PHYD32CLKA;

	}

}



static int get_odm_segment_count(struct pipe_ctx *pipe_ctx)

{

	struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

	int count = 1;



	while (odm_pipe != NULL) {

		count++;

		odm_pipe = odm_pipe->next_odm_pipe;

	}



	return count;

}



enum dc_status dcn20_enable_stream_timing(

		struct pipe_ctx *pipe_ctx,

		struct dc_state *context,
@@ -817,6 +848,23 @@ enum dc_status dcn20_enable_stream_timing( 
		if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)

			pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);

	}



	if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

		struct dccg *dccg = dc->res_pool->dccg;

		struct timing_generator *tg = pipe_ctx->stream_res.tg;

		struct dtbclk_dto_params dto_params = {0};



		if (dccg->funcs->set_dtbclk_p_src)

			dccg->funcs->set_dtbclk_p_src(dccg, DTBCLK0, tg->inst);



		dto_params.otg_inst = tg->inst;

		dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;

		dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);

		dto_params.timing = &pipe_ctx->stream->timing;

		dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

		dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

	}



	return DC_OK;

}
@@ -2659,37 +2707,6 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 
	hubp->mpcc_id = mpcc_id;

}



static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)

{

	switch (link->link_enc->transmitter) {

	case TRANSMITTER_UNIPHY_A:

		return PHYD32CLKA;

	case TRANSMITTER_UNIPHY_B:

		return PHYD32CLKB;

	case TRANSMITTER_UNIPHY_C:

		return PHYD32CLKC;

	case TRANSMITTER_UNIPHY_D:

		return PHYD32CLKD;

	case TRANSMITTER_UNIPHY_E:

		return PHYD32CLKE;

	default:

		return PHYD32CLKA;

	}

}



static int get_odm_segment_count(struct pipe_ctx *pipe_ctx)

{

	struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

	int count = 1;



	while (odm_pipe != NULL) {

		count++;

		odm_pipe = odm_pipe->next_odm_pipe;

	}



	return count;

}



void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)

{

	enum dc_lane_count lane_count =

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c

+1 −0
Original line number Diff line number Diff line
@@ -375,6 +375,7 @@ static const struct dccg_funcs dccg314_funcs = { 
	.set_pixel_rate_div = dccg314_set_pixel_rate_div,

	.trigger_dio_fifo_resync = dccg314_trigger_dio_fifo_resync,

	.set_valid_pixel_rate = dccg314_set_valid_pixel_rate,

	.set_dtbclk_p_src = dccg314_set_dtbclk_p_src

};



struct dccg *dccg314_create(

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c

+1 −0
Original line number Diff line number Diff line
@@ -345,6 +345,7 @@ static const struct dccg_funcs dccg32_funcs = { 
	.otg_drop_pixel = dccg32_otg_drop_pixel,

	.set_pixel_rate_div = dccg32_set_pixel_rate_div,

	.trigger_dio_fifo_resync = dccg32_trigger_dio_fifo_resync,

	.set_dtbclk_p_src = dccg32_set_dtbclk_p_src,

};



struct dccg *dccg32_create(

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c

+1 −0
Original line number Diff line number Diff line
@@ -767,6 +767,7 @@ static const struct dccg_funcs dccg35_funcs = { 
	.set_valid_pixel_rate = dccg35_set_valid_pixel_rate,

	.enable_symclk_se = dccg35_enable_symclk_se,

	.disable_symclk_se = dccg35_disable_symclk_se,

	.set_dtbclk_p_src = dccg35_set_dtbclk_p_src,

};



struct dccg *dccg35_create(

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

+4 −0
Original line number Diff line number Diff line
@@ -192,6 +192,10 @@ struct dccg_funcs { 
	void (*set_dp_dto)(

			struct dccg *dccg,

			const struct dp_dto_params *params);

	void (*set_dtbclk_p_src)(

			struct dccg *dccg,

			enum streamclk_source src,

			uint32_t otg_inst);

};



#endif //__DAL_DCCG_H__