Commit ce7577a2 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/pp: split out common smumgr smu9 code 



Split out the shared smumgr code for vega10 and 12
so we don't have duplicate code for both.

Reviewed-by: default avatarRex Zhu <rezhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 26094c02

drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

+15 −29
Original line number Diff line number Diff line
@@ -477,7 +477,7 @@ static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr, 
			"[GetNumOfDpmLevel] failed to get dpm levels!",

			return ret);



	vega12_read_arg_from_smc(hwmgr, num_of_levels);

	*num_of_levels = smum_get_argument(hwmgr);

	PP_ASSERT_WITH_CODE(*num_of_levels > 0,

			"[GetNumOfDpmLevel] number of clk levels is invalid!",

			return -EINVAL);
@@ -499,11 +499,7 @@ static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, 
		"[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!",

		return -EINVAL);



	result = vega12_read_arg_from_smc(hwmgr, clock);



	PP_ASSERT_WITH_CODE(*clock != 0,

		"[GetDPMFrequencyByIndex] Failed to get dpm frequency by index.!",

		return -EINVAL);

	*clock = smum_get_argument(hwmgr);



	return result;

}
@@ -884,21 +880,21 @@ static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr, 
		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16)) == 0,

		"[GetClockRanges] Failed to get max ac clock from SMC!",

		return -EINVAL);

	vega12_read_arg_from_smc(hwmgr, &(clock->ACMax));

	clock->ACMax = smum_get_argument(hwmgr);



	/* AC Min */

	PP_ASSERT_WITH_CODE(

		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16)) == 0,

		"[GetClockRanges] Failed to get min ac clock from SMC!",

		return -EINVAL);

	vega12_read_arg_from_smc(hwmgr, &(clock->ACMin));

	clock->ACMin = smum_get_argument(hwmgr);



	/* DC Max */

	PP_ASSERT_WITH_CODE(

		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16)) == 0,

		"[GetClockRanges] Failed to get max dc clock from SMC!",

		return -EINVAL);

	vega12_read_arg_from_smc(hwmgr, &(clock->DCMax));

	clock->DCMax = smum_get_argument(hwmgr);



	return 0;

}
@@ -1219,7 +1215,7 @@ static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query) 
			"Failed to get current package power!",

			return -EINVAL);



	vega12_read_arg_from_smc(hwmgr, &value);

	value = smum_get_argument(hwmgr);

	/* power value is an integer */

	*query = value << 8;

#endif
@@ -1235,11 +1231,8 @@ static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx 
	PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,

			PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16)) == 0,

			"[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!",

			return -1);

	PP_ASSERT_WITH_CODE(

			vega12_read_arg_from_smc(hwmgr, &gfx_clk) == 0,

			"[GetCurrentGfxClkFreq] Attempt to read arg from SMC Failed",

			return -1);

			return -EINVAL);

	gfx_clk = smum_get_argument(hwmgr);



	*gfx_freq = gfx_clk * 100;
@@ -1255,11 +1248,8 @@ static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_f 
	PP_ASSERT_WITH_CODE(

			smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16)) == 0,

			"[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!",

			return -1);

	PP_ASSERT_WITH_CODE(

			vega12_read_arg_from_smc(hwmgr, &mem_clk) == 0,

			"[GetCurrentMClkFreq] Attempt to read arg from SMC Failed",

			return -1);

			return -EINVAL);

	mem_clk = smum_get_argument(hwmgr);



	*mclk_freq = mem_clk * 100;
@@ -1276,16 +1266,12 @@ static int vega12_get_current_activity_percent( 
#if 0

	ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);

	if (!ret) {

		ret = vega12_read_arg_from_smc(hwmgr, &current_activity);

		if (!ret) {

		current_activity = smum_get_argument(hwmgr);

		if (current_activity > 100) {

			PP_ASSERT(false,

				  "[GetCurrentActivityPercent] Activity Percentage Exceeds 100!");

			current_activity = 100;

		}

		} else

			PP_ASSERT(false,

				"[GetCurrentActivityPercent] Attempt To Read Average Graphics Activity from SMU Failed!");

	} else

		PP_ASSERT(false,

			"[GetCurrentActivityPercent] Attempt To Send Get Average Graphics Activity to SMU Failed!");

drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c

+3 −5
Original line number Diff line number Diff line
@@ -34,11 +34,9 @@ static int vega12_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) 
	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,

				PPSMC_MSG_GetCurrentRpm),

			"Attempt to get current RPM from SMC Failed!",

			return -1);

	PP_ASSERT_WITH_CODE(!vega12_read_arg_from_smc(hwmgr,

			current_rpm),

			"Attempt to read current RPM from SMC Failed!",

			return -1);

			return -EINVAL);

	*current_rpm = smum_get_argument(hwmgr);



	return 0;

}

drivers/gpu/drm/amd/powerplay/smumgr/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ 
SMU_MGR = smumgr.o smu8_smumgr.o tonga_smumgr.o fiji_smumgr.o \

	  polaris10_smumgr.o iceland_smumgr.o \

	  smu7_smumgr.o vega10_smumgr.o smu10_smumgr.o ci_smumgr.o \

	  vega12_smumgr.o vegam_smumgr.o

	  vega12_smumgr.o vegam_smumgr.o smu9_smumgr.o



AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))

drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c

0 → 100644
+150 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2018 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#include "smumgr.h"

#include "vega10_inc.h"

#include "soc15_common.h"

#include "pp_debug.h"





/* MP Apertures */

#define MP0_Public                  0x03800000

#define MP0_SRAM                    0x03900000

#define MP1_Public                  0x03b00000

#define MP1_SRAM                    0x03c00004



#define smnMP1_FIRMWARE_FLAGS                                                                           0x3010028



bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr)

{

	struct amdgpu_device *adev = hwmgr->adev;

	uint32_t mp1_fw_flags;



	WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2,

			(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));



	mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2);



	if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)

		return true;



	return false;

}



/*

 * Check if SMC has responded to previous message.

 *

 * @param    smumgr  the address of the powerplay hardware manager.

 * @return   TRUE    SMC has responded, FALSE otherwise.

 */

static uint32_t smu9_wait_for_response(struct pp_hwmgr *hwmgr)

{

	struct amdgpu_device *adev = hwmgr->adev;

	uint32_t reg;

	uint32_t ret;



	reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);



	ret = phm_wait_for_register_unequal(hwmgr, reg,

			0, MP1_C2PMSG_90__CONTENT_MASK);



	if (ret)

		pr_err("No response from smu\n");



	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);

}



/*

 * Send a message to the SMC, and do not wait for its response.

 * @param    smumgr  the address of the powerplay hardware manager.

 * @param    msg the message to send.

 * @return   Always return 0.

 */

static int smu9_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,

						uint16_t msg)

{

	struct amdgpu_device *adev = hwmgr->adev;



	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);



	return 0;

}



/*

 * Send a message to the SMC, and wait for its response.

 * @param    hwmgr  the address of the powerplay hardware manager.

 * @param    msg the message to send.

 * @return   Always return 0.

 */

int smu9_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)

{

	struct amdgpu_device *adev = hwmgr->adev;

	uint32_t ret;



	smu9_wait_for_response(hwmgr);



	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);



	smu9_send_msg_to_smc_without_waiting(hwmgr, msg);



	ret = smu9_wait_for_response(hwmgr);

	if (ret != 1)

		pr_err("Failed to send message: 0x%x, ret value: 0x%x\n", msg, ret);



	return 0;

}



/*

 * Send a message to the SMC with parameter

 * @param    hwmgr:  the address of the powerplay hardware manager.

 * @param    msg: the message to send.

 * @param    parameter: the parameter to send

 * @return   Always return 0.

 */

int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,

					uint16_t msg, uint32_t parameter)

{

	struct amdgpu_device *adev = hwmgr->adev;

	uint32_t ret;



	smu9_wait_for_response(hwmgr);



	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);



	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);



	smu9_send_msg_to_smc_without_waiting(hwmgr, msg);



	ret = smu9_wait_for_response(hwmgr);

	if (ret != 1)

		pr_err("Failed message: 0x%x, input parameter: 0x%x, error code: 0x%x\n", msg, parameter, ret);



	return 0;

}



int smu9_get_argument(struct pp_hwmgr *hwmgr)

{

	struct amdgpu_device *adev = hwmgr->adev;



	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);

}

drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h

0 → 100644
+32 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2018 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef _SMU9_SMUMANAGER_H_

#define _SMU9_SMUMANAGER_H_



bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr);

int smu9_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);

int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,

					uint16_t msg, uint32_t parameter);

int smu9_get_argument(struct pp_hwmgr *hwmgr);



#endif