Commit ce8bf5bd authored by Lucas De Marchi's avatar Lucas De Marchi Committed by Rodrigo Vivi
Browse files

drm/xe/mmio: Use struct xe_reg 



Convert all the callers to deal with xe_mmio_*() using struct xe_reg
instead of plain u32. In a few places there was also a rename
s/reg/reg_val/ when dealing with the value returned so it doesn't get
mixed up with the register address.

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/20230508225322.2692066-2-lucas.demarchi@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 34f89ac8

drivers/gpu/drm/xe/xe_device.c

+1 −1
Original line number Diff line number Diff line
@@ -345,7 +345,7 @@ void xe_device_wmb(struct xe_device *xe) 


	wmb();

	if (IS_DGFX(xe))

		xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33.reg, 0);

		xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33, 0);

}



u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size)

drivers/gpu/drm/xe/xe_execlist.c

+9 −9
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc, 
	}



	if (hwe->class == XE_ENGINE_CLASS_COMPUTE)

		xe_mmio_write32(hwe->gt, RCU_MODE.reg,

		xe_mmio_write32(hwe->gt, RCU_MODE,

				_MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));



	xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
@@ -78,17 +78,17 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc, 
	 */

	wmb();



	xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base).reg,

	xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base),

			xe_bo_ggtt_addr(hwe->hwsp));

	xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base).reg);

	xe_mmio_write32(gt, RING_MODE(hwe->mmio_base).reg,

	xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base));

	xe_mmio_write32(gt, RING_MODE(hwe->mmio_base),

			_MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));



	xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base).reg,

	xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),

			lower_32_bits(lrc_desc));

	xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base).reg,

	xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base),

			upper_32_bits(lrc_desc));

	xe_mmio_write32(gt, RING_EXECLIST_CONTROL(hwe->mmio_base).reg,

	xe_mmio_write32(gt, RING_EXECLIST_CONTROL(hwe->mmio_base),

			EL_CTRL_LOAD);

}
@@ -173,8 +173,8 @@ static u64 read_execlist_status(struct xe_hw_engine *hwe) 
	struct xe_gt *gt = hwe->gt;

	u32 hi, lo;



	lo = xe_mmio_read32(gt, RING_EXECLIST_STATUS_LO(hwe->mmio_base).reg);

	hi = xe_mmio_read32(gt, RING_EXECLIST_STATUS_HI(hwe->mmio_base).reg);

	lo = xe_mmio_read32(gt, RING_EXECLIST_STATUS_LO(hwe->mmio_base));

	hi = xe_mmio_read32(gt, RING_EXECLIST_STATUS_HI(hwe->mmio_base));



	printk(KERN_INFO "EXECLIST_STATUS %d:%d = 0x%08x %08x\n", hwe->class,

	       hwe->instance, hi, lo);

drivers/gpu/drm/xe/xe_force_wake.c

+13 −12
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <drm/drm_util.h>



#include "regs/xe_gt_regs.h"

#include "regs/xe_reg_defs.h"

#include "xe_gt.h"

#include "xe_mmio.h"
@@ -27,7 +28,7 @@ fw_to_xe(struct xe_force_wake *fw) 


static void domain_init(struct xe_force_wake_domain *domain,

			enum xe_force_wake_domain_id id,

			u32 reg, u32 ack, u32 val, u32 mask)

			struct xe_reg reg, struct xe_reg ack, u32 val, u32 mask)

{

	domain->id = id;

	domain->reg_ctl = reg;
@@ -49,14 +50,14 @@ void xe_force_wake_init_gt(struct xe_gt *gt, struct xe_force_wake *fw) 
	if (xe->info.graphics_verx100 >= 1270) {

		domain_init(&fw->domains[XE_FW_DOMAIN_ID_GT],

			    XE_FW_DOMAIN_ID_GT,

			    FORCEWAKE_GT.reg,

			    FORCEWAKE_ACK_GT_MTL.reg,

			    FORCEWAKE_GT,

			    FORCEWAKE_ACK_GT_MTL,

			    BIT(0), BIT(16));

	} else {

		domain_init(&fw->domains[XE_FW_DOMAIN_ID_GT],

			    XE_FW_DOMAIN_ID_GT,

			    FORCEWAKE_GT.reg,

			    FORCEWAKE_ACK_GT.reg,

			    FORCEWAKE_GT,

			    FORCEWAKE_ACK_GT,

			    BIT(0), BIT(16));

	}

}
@@ -71,8 +72,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw) 
	if (!xe_gt_is_media_type(gt))

		domain_init(&fw->domains[XE_FW_DOMAIN_ID_RENDER],

			    XE_FW_DOMAIN_ID_RENDER,

			    FORCEWAKE_RENDER.reg,

			    FORCEWAKE_ACK_RENDER.reg,

			    FORCEWAKE_RENDER,

			    FORCEWAKE_ACK_RENDER,

			    BIT(0), BIT(16));



	for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
@@ -81,8 +82,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw) 


		domain_init(&fw->domains[XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j],

			    XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j,

			    FORCEWAKE_MEDIA_VDBOX(j).reg,

			    FORCEWAKE_ACK_MEDIA_VDBOX(j).reg,

			    FORCEWAKE_MEDIA_VDBOX(j),

			    FORCEWAKE_ACK_MEDIA_VDBOX(j),

			    BIT(0), BIT(16));

	}
@@ -92,8 +93,8 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw) 


		domain_init(&fw->domains[XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j],

			    XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j,

			    FORCEWAKE_MEDIA_VEBOX(j).reg,

			    FORCEWAKE_ACK_MEDIA_VEBOX(j).reg,

			    FORCEWAKE_MEDIA_VEBOX(j),

			    FORCEWAKE_ACK_MEDIA_VEBOX(j),

			    BIT(0), BIT(16));

	}

}
@@ -128,7 +129,7 @@ static int domain_sleep_wait(struct xe_gt *gt, 
	for (tmp__ = (mask__); tmp__; tmp__ &= ~BIT(ffs(tmp__) - 1)) \

		for_each_if((domain__ = ((fw__)->domains + \

					 (ffs(tmp__) - 1))) && \

					 domain__->reg_ctl)

					 domain__->reg_ctl.reg)



int xe_force_wake_get(struct xe_force_wake *fw,

		      enum xe_force_wake_domains domains)

drivers/gpu/drm/xe/xe_force_wake_types.h

+4 −2
Original line number Diff line number Diff line
@@ -9,6 +9,8 @@ 
#include <linux/mutex.h>

#include <linux/types.h>



#include "regs/xe_reg_defs.h"



enum xe_force_wake_domain_id {

	XE_FW_DOMAIN_ID_GT = 0,

	XE_FW_DOMAIN_ID_RENDER,
@@ -56,9 +58,9 @@ struct xe_force_wake_domain { 
	/** @id: domain force wake id */

	enum xe_force_wake_domain_id id;

	/** @reg_ctl: domain wake control register address */

	u32 reg_ctl;

	struct xe_reg reg_ctl;

	/** @reg_ack: domain ack register address */

	u32 reg_ack;

	struct xe_reg reg_ack;

	/** @val: domain wake write value */

	u32 val;

	/** @mask: domain mask */

drivers/gpu/drm/xe/xe_ggtt.c

+3 −3
Original line number Diff line number Diff line
@@ -207,12 +207,12 @@ void xe_ggtt_invalidate(struct xe_gt *gt) 
		struct xe_device *xe = gt_to_xe(gt);



		if (xe->info.platform == XE_PVC) {

			xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC1.reg,

			xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC1,

					PVC_GUC_TLB_INV_DESC1_INVALIDATE);

			xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0.reg,

			xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0,

					PVC_GUC_TLB_INV_DESC0_VALID);

		} else

			xe_mmio_write32(gt, GUC_TLB_INV_CR.reg,

			xe_mmio_write32(gt, GUC_TLB_INV_CR,

					GUC_TLB_INV_CR_INVALIDATE);

	}

}