Commit cec82816 authored by Vinay Belgaumkar's avatar Vinay Belgaumkar Committed by John Harrison
Browse files

drm/i915/guc: Use context hints for GT frequency 

Allow user to provide a low latency context hint. When set, KMD
sends a hint to GuC which results in special handling for this
context. SLPC will ramp the GT frequency aggressively every time
it switches to this context. The down freq threshold will also be
lower so GuC will ramp down the GT freq for this context more slowly.
We also disable waitboost for this context as that will interfere with
the strategy.

We need to enable the use of SLPC Compute strategy during init, but
it will apply only to contexts that set this bit during context
creation.

Userland can check whether this feature is supported using a new param-
I915_PARAM_HAS_CONTEXT_FREQ_HINT. This flag is true for all guc submission
enabled platforms as they use SLPC for frequency management.

The Mesa usage model for this flag is here -
https://gitlab.freedesktop.org/sushmave/mesa/-/commits/compute_hint



v2: Rename flags as per review suggestions (Rodrigo, Tvrtko).
Also, use flag bits in intel_context as it allows finer control for
toggling per engine if needed (Tvrtko).

v3: Minor review comments (Tvrtko)

v4: Update comment (Sushma)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: default avatarIvan Briano <ivan.briano@intel.com>
Signed-off-by: default avatarVinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240306012759.204938-1-vinay.belgaumkar@intel.com
parent 71271280

drivers/gpu/drm/i915/gem/i915_gem_context.c

+14 −2
Original line number Diff line number Diff line
@@ -879,6 +879,7 @@ static int set_proto_ctx_param(struct drm_i915_file_private *fpriv, 
			       struct i915_gem_proto_context *pc,

			       struct drm_i915_gem_context_param *args)

{

	struct drm_i915_private *i915 = fpriv->i915;

	int ret = 0;



	switch (args->param) {
@@ -904,6 +905,13 @@ static int set_proto_ctx_param(struct drm_i915_file_private *fpriv, 
			pc->user_flags &= ~BIT(UCONTEXT_BANNABLE);

		break;



	case I915_CONTEXT_PARAM_LOW_LATENCY:

		if (intel_uc_uses_guc_submission(&to_gt(i915)->uc))

			pc->user_flags |= BIT(UCONTEXT_LOW_LATENCY);

		else

			ret = -EINVAL;

		break;



	case I915_CONTEXT_PARAM_RECOVERABLE:

		if (args->size)

			ret = -EINVAL;
@@ -992,6 +1000,9 @@ static int intel_context_set_gem(struct intel_context *ce, 
	if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS))

		ret = intel_context_reconfigure_sseu(ce, sseu);



	if (test_bit(UCONTEXT_LOW_LATENCY, &ctx->user_flags))

		__set_bit(CONTEXT_LOW_LATENCY, &ce->flags);



	return ret;

}
@@ -1630,6 +1641,9 @@ i915_gem_create_context(struct drm_i915_private *i915, 
	if (vm)

		ctx->vm = vm;



	/* Assign early so intel_context_set_gem can access these flags */

	ctx->user_flags = pc->user_flags;



	mutex_init(&ctx->engines_mutex);

	if (pc->num_user_engines >= 0) {

		i915_gem_context_set_user_engines(ctx);
@@ -1652,8 +1666,6 @@ i915_gem_create_context(struct drm_i915_private *i915, 
	 * is no remap info, it will be a NOP. */

	ctx->remap_slice = ALL_L3_SLICES(i915);



	ctx->user_flags = pc->user_flags;



	for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)

		ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;

drivers/gpu/drm/i915/gem/i915_gem_context_types.h

+1 −0
Original line number Diff line number Diff line
@@ -338,6 +338,7 @@ struct i915_gem_context { 
#define UCONTEXT_BANNABLE		2

#define UCONTEXT_RECOVERABLE		3

#define UCONTEXT_PERSISTENCE		4

#define UCONTEXT_LOW_LATENCY		5



	/**

	 * @flags: small set of booleans

drivers/gpu/drm/i915/gt/intel_context_types.h

+1 −0
Original line number Diff line number Diff line
@@ -130,6 +130,7 @@ struct intel_context { 
#define CONTEXT_PERMA_PIN		11

#define CONTEXT_IS_PARKING		12

#define CONTEXT_EXITING			13

#define CONTEXT_LOW_LATENCY		14



	struct {

		u64 timeout_us;

drivers/gpu/drm/i915/gt/intel_rps.c

+4 −0
Original line number Diff line number Diff line
@@ -1013,6 +1013,10 @@ void intel_rps_boost(struct i915_request *rq) 
	if (i915_request_signaled(rq) || i915_request_has_waitboost(rq))

		return;



	/* Waitboost is not needed for contexts marked with a Freq hint */

	if (test_bit(CONTEXT_LOW_LATENCY, &rq->context->flags))

		return;



	/* Serializes with i915_request_retire() */

	if (!test_and_set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags)) {

		struct intel_rps *rps = &READ_ONCE(rq->engine)->gt->rps;

drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

+21 −0
Original line number Diff line number Diff line
@@ -207,6 +207,27 @@ struct slpc_shared_data { 
	u8 reserved_mode_definition[4096];

} __packed;



struct slpc_context_frequency_request {

	u32 frequency_request:16;

	u32 reserved:12;

	u32 is_compute:1;

	u32 ignore_busyness:1;

	u32 is_minimum:1;

	u32 is_predefined:1;

} __packed;



#define SLPC_CTX_FREQ_REQ_IS_COMPUTE		REG_BIT(28)



struct slpc_optimized_strategies {

	u32 compute:1;

	u32 async_flip:1;

	u32 media:1;

	u32 vsync_flip:1;

	u32 reserved:28;

} __packed;



#define SLPC_OPTIMIZED_STRATEGY_COMPUTE		REG_BIT(0)



/**

 * DOC: SLPC H2G MESSAGE FORMAT

 *