Commit cf1aa9ff authored by Boyuan Zhang's avatar Boyuan Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: move per inst variables to amdgpu_vcn_inst 



Move all per instance variables from amdgpu_vcn to amdgpu_vcn_inst.

Move adev->vcn.fw[i] from amdgpu_vcn to amdgpu_vcn_inst.
Move adev->vcn.vcn_config[i] from amdgpu_vcn to amdgpu_vcn_inst.
Move adev->vcn.vcn_codec_disable_mask[i] from amdgpu_vcn to amdgpu_vcn_inst.

Signed-off-by: default avatarBoyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f2ba8c3d

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+2 −2
Original line number Diff line number Diff line
@@ -1340,7 +1340,7 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 
				 */

				if (adev->vcn.num_vcn_inst <

				    AMDGPU_MAX_VCN_INSTANCES) {

					adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =

					adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config =

						ip->revision & 0xc0;

					adev->vcn.num_vcn_inst++;

					adev->vcn.inst_mask |=
@@ -1705,7 +1705,7 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 
		 * so this won't overflow.

		 */

		for (v = 0; v < adev->vcn.num_vcn_inst; v++) {

			adev->vcn.vcn_codec_disable_mask[v] =

			adev->vcn.inst[v].vcn_codec_disable_mask =

				le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);

		}

		break;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

+10 −10
Original line number Diff line number Diff line
@@ -99,11 +99,11 @@ int amdgpu_vcn_early_init(struct amdgpu_device *adev) 
	amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));

	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {

		if (i == 1 && amdgpu_ip_version(adev, UVD_HWIP, 0) ==  IP_VERSION(4, 0, 6))

			r = amdgpu_ucode_request(adev, &adev->vcn.fw[i], "amdgpu/%s_%d.bin", ucode_prefix, i);

			r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, "amdgpu/%s_%d.bin", ucode_prefix, i);

		else

			r = amdgpu_ucode_request(adev, &adev->vcn.fw[i], "amdgpu/%s.bin", ucode_prefix);

			r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, "amdgpu/%s.bin", ucode_prefix);

		if (r) {

			amdgpu_ucode_release(&adev->vcn.fw[i]);

			amdgpu_ucode_release(&adev->vcn.inst[i].fw);

			return r;

		}

	}
@@ -151,7 +151,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 
	adev->vcn.using_unified_queue =

		amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0);



	hdr = (const struct common_firmware_header *)adev->vcn.fw[0]->data;

	hdr = (const struct common_firmware_header *)adev->vcn.inst[0].fw->data;

	adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);



	/* Bit 20-23, it is encode major and non-zero for new naming convention.
@@ -270,7 +270,7 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 
		for (i = 0; i < adev->vcn.num_enc_rings; ++i)

			amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);



		amdgpu_ucode_release(&adev->vcn.fw[j]);

		amdgpu_ucode_release(&adev->vcn.inst[j].fw);

	}



	mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
@@ -282,7 +282,7 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 
bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)

{

	bool ret = false;

	int vcn_config = adev->vcn.vcn_config[vcn_instance];

	int vcn_config = adev->vcn.inst[vcn_instance].vcn_config;



	if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK))

		ret = true;
@@ -362,12 +362,12 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev) 
			const struct common_firmware_header *hdr;

			unsigned int offset;



			hdr = (const struct common_firmware_header *)adev->vcn.fw[i]->data;

			hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;

			if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {

				offset = le32_to_cpu(hdr->ucode_array_offset_bytes);

				if (drm_dev_enter(adev_to_drm(adev), &idx)) {

					memcpy_toio(adev->vcn.inst[i].cpu_addr,

						    adev->vcn.fw[i]->data + offset,

						    adev->vcn.inst[i].fw->data + offset,

						    le32_to_cpu(hdr->ucode_size_bytes));

					drm_dev_exit(idx);

				}
@@ -1063,7 +1063,7 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 
			if (adev->vcn.harvest_config & (1 << i))

				continue;



			hdr = (const struct common_firmware_header *)adev->vcn.fw[i]->data;

			hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;

			/* currently only support 2 FW instances */

			if (i >= 2) {

				dev_info(adev->dev, "More then 2 VCN FW instances!\n");
@@ -1071,7 +1071,7 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev) 
			}

			idx = AMDGPU_UCODE_ID_VCN + i;

			adev->firmware.ucode[idx].ucode_id = idx;

			adev->firmware.ucode[idx].fw = adev->vcn.fw[i];

			adev->firmware.ucode[idx].fw = adev->vcn.inst[i].fw;

			adev->firmware.fw_size +=

				ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+3 −3
Original line number Diff line number Diff line
@@ -297,6 +297,9 @@ struct amdgpu_vcn_inst { 
	atomic_t		dpg_enc_submission_cnt;

	struct amdgpu_vcn_fw_shared fw_shared;

	uint8_t			aid_id;

	const struct firmware	*fw; /* VCN firmware */

	uint8_t			vcn_config;

	uint32_t		vcn_codec_disable_mask;

};



struct amdgpu_vcn_ras {
@@ -306,15 +309,12 @@ struct amdgpu_vcn_ras { 
struct amdgpu_vcn {

	unsigned		fw_version;

	struct delayed_work	idle_work;

	const struct firmware	*fw[AMDGPU_MAX_VCN_INSTANCES];	/* VCN firmware */

	unsigned		num_enc_rings;

	enum amd_powergating_state cur_state;

	bool			indirect_sram;



	uint8_t	num_vcn_inst;

	struct amdgpu_vcn_inst	 inst[AMDGPU_MAX_VCN_INSTANCES];

	uint8_t			 vcn_config[AMDGPU_MAX_VCN_INSTANCES];

	uint32_t		 vcn_codec_disable_mask[AMDGPU_MAX_VCN_INSTANCES];

	struct amdgpu_vcn_reg	 internal;

	struct mutex		 vcn_pg_lock;

	struct mutex		vcn1_jpeg1_workaround;

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

+2 −2
Original line number Diff line number Diff line
@@ -345,7 +345,7 @@ static int vcn_v1_0_resume(struct amdgpu_ip_block *ip_block) 
 */

static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)

{

	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);

	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);

	uint32_t offset;



	/* cache window 0: fw */
@@ -412,7 +412,7 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 


static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)

{

	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);

	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);

	uint32_t offset;



	/* cache window 0: fw */

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

+3 −3
Original line number Diff line number Diff line
@@ -372,7 +372,7 @@ static int vcn_v2_0_resume(struct amdgpu_ip_block *ip_block) 
 */

static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)

{

	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);

	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);

	uint32_t offset;



	if (amdgpu_sriov_vf(adev))
@@ -428,7 +428,7 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev) 


static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)

{

	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);

	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);

	uint32_t offset;



	/* cache window 0: fw */
@@ -1920,7 +1920,7 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) 


		init_table += header->vcn_table_offset;



		size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);

		size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);



		MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(

			SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),