Commit cf1aaa7d authored by Danylo Piliaiev's avatar Danylo Piliaiev Committed by Rob Clark
Browse files

drm/msm/a6xx: Add missing BIT(7) to REG_A6XX_UCHE_CLIENT_PF 



Downstream always set BIT(7)

Signed-off-by: default avatarDanylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/568930/
parent 6c15808d

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -1782,7 +1782,7 @@ static int hw_init(struct msm_gpu *gpu) 
	else

		gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff);



	gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);

	gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1);



	/* Set weights for bicubic filtering */

	if (adreno_is_a650_family(adreno_gpu)) {