Commit cf37495a authored by Luca Coelho's avatar Luca Coelho
Browse files

drm/i915: move LPT clock gating init into intel_pch 



Move the LPT PCH clock gating programming into
intel_pch_init_clock_gating() and switch the corresponding
Haswell/Broadwell callers to the display-specific code.

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260324080441.154609-4-luciano.coelho@intel.com


Signed-off-by: default avatarLuca Coelho <luciano.coelho@intel.com>
parent d129bce3

drivers/gpu/drm/i915/display/intel_pch.c

+19 −0
Original line number Diff line number Diff line
@@ -264,6 +264,21 @@ static void intel_pch_cpt_init_clock_gating(struct intel_display *display) 
			       TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);

}



static void intel_pch_lpt_init_clock_gating(struct intel_display *display)

{

	/*

	 * TODO: this bit should only be enabled when really needed, then

	 * disabled when not needed anymore in order to save power.

	 */

	if (HAS_PCH_LPT_LP(display))

		intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,

			     PCH_LP_PARTITION_LEVEL_DISABLE);



	/* WADPOClockGatingDisable:hsw */

	intel_de_rmw(display, TRANS_CHICKEN1(PIPE_A), 0,

		     TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);

}



void intel_pch_init_clock_gating(struct intel_display *display)

{

	switch (INTEL_PCH_TYPE(display)) {
@@ -273,6 +288,10 @@ void intel_pch_init_clock_gating(struct intel_display *display) 
	case PCH_CPT:

		intel_pch_cpt_init_clock_gating(display);

		break;

	case PCH_LPT_H:

	case PCH_LPT_LP:

		intel_pch_lpt_init_clock_gating(display);

		break;

	default:

		break;

	}

drivers/gpu/drm/i915/intel_clock_gating.c

+2 −19
Original line number Diff line number Diff line
@@ -266,23 +266,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *i915) 
	gen6_check_mch_setup(i915);

}



static void lpt_init_clock_gating(struct drm_i915_private *i915)

{

	struct intel_display *display = i915->display;



	/*

	 * TODO: this bit should only be enabled when really needed, then

	 * disabled when not needed anymore in order to save power.

	 */

	if (HAS_PCH_LPT_LP(display))

		intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D,

				 0, PCH_LP_PARTITION_LEVEL_DISABLE);



	/* WADPOClockGatingDisable:hsw */

	intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A),

			 0, TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);

}



static void gen8_set_l3sqc_credits(struct drm_i915_private *i915,

				   int general_prio_credits,

				   int high_prio_credits)
@@ -422,7 +405,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915) 
	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1,

			 0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);



	lpt_init_clock_gating(i915);

	intel_pch_init_clock_gating(i915->display);



	/* WaDisableDopClockGating:bdw

	 *
@@ -456,7 +439,7 @@ static void hsw_init_clock_gating(struct drm_i915_private *i915) 
	/* WaSwitchSolVfFArbitrationPriority:hsw */

	intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);



	lpt_init_clock_gating(i915);

	intel_pch_init_clock_gating(i915->display);

}



static void ivb_init_clock_gating(struct drm_i915_private *i915)