Commit cf938f91 authored by Seongsu Park's avatar Seongsu Park Committed by Catalin Marinas
Browse files

arm64: Cleanup __cpu_set_tcr_t0sz() 



The T0SZ field of TCR_EL1 occupies bits 0-5 of the register and encode
the virtual address space translated by TTBR0_EL1. When updating the
field, for example because we are switching to/from the idmap page-table,
__cpu_set_tcr_t0sz() erroneously treats its 't0sz' argument as unshifted,
resulting in harmless but confusing double shifts by 0 in the code.

Co-developed-by: default avatarLeem ChaeHoon <infinite.run@gmail.com>
Signed-off-by: default avatarLeem ChaeHoon <infinite.run@gmail.com>
Signed-off-by: default avatarSeongsu Park <sgsu.park@samsung.com>
Link: https://lore.kernel.org/r/20240523122146.144483-1-sgsu.park@samsung.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 57361114

arch/arm64/include/asm/mmu_context.h

+2 −2
Original line number Diff line number Diff line
@@ -72,11 +72,11 @@ static inline void __cpu_set_tcr_t0sz(unsigned long t0sz) 
{

	unsigned long tcr = read_sysreg(tcr_el1);



	if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz)

	if ((tcr & TCR_T0SZ_MASK) == t0sz)

		return;



	tcr &= ~TCR_T0SZ_MASK;

	tcr |= t0sz << TCR_T0SZ_OFFSET;

	tcr |= t0sz;

	write_sysreg(tcr, tcr_el1);

	isb();

}