Commit d00b42f1 authored by Neil Armstrong's avatar Neil Armstrong Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk 



The PCIe Gen4x2 PHY found in the SM8650 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.

Remove the dummy pcie-1-phy-aux-clk clock and now the pcie1_phy exposes
2 clocks, properly add the pcie1_phy provided clocks to the Global Clock
Controller (GCC) node clocks inputs.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-3-10c650cfeade@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 0cc97d9e

arch/arm64/boot/dts/qcom/sm8650-mtp.dts

+0 −4
Original line number Diff line number Diff line
@@ -641,10 +641,6 @@ &mdss_dsi0_phy { 
	status = "okay";

};



&pcie_1_phy_aux_clk {

	clock-frequency = <1000>;

};



&pcie0 {

	wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;

	perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;

arch/arm64/boot/dts/qcom/sm8650-qrd.dts

+0 −4
Original line number Diff line number Diff line
@@ -834,10 +834,6 @@ &mdss_dp0_out { 
	data-lanes = <0 1>;

};



&pcie_1_phy_aux_clk {

	clock-frequency = <1000>;

};



&pcie0 {

	wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;

	perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;

arch/arm64/boot/dts/qcom/sm8650.dtsi

+4 −9
Original line number Diff line number Diff line
@@ -60,11 +60,6 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 
			clock-mult = <1>;

			clock-div = <2>;

		};



		pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

		};

	};



	cpus {
@@ -758,8 +753,8 @@ gcc: clock-controller@100000 { 
				 <&bi_tcxo_ao_div2>,

				 <&sleep_clk>,

				 <&pcie0_phy>,

				 <&pcie1_phy>,

				 <&pcie_1_phy_aux_clk>,

				 <&pcie1_phy QMP_PCIE_PIPE_CLK>,

				 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,

				 <&ufs_mem_phy 0>,

				 <&ufs_mem_phy 1>,

				 <&ufs_mem_phy 2>,
@@ -2467,8 +2462,8 @@ pcie1_phy: phy@1c0e000 { 


			power-domains = <&gcc PCIE_1_PHY_GDSC>;



			#clock-cells = <0>;

			clock-output-names = "pcie1_pipe_clk";

			#clock-cells = <1>;

			clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk";



			#phy-cells = <0>;