Commit d0855575 authored by Chun-Kuang Hu's avatar Chun-Kuang Hu
Browse files

Revert "drm/mediatek: dsi: Correct calculation formula of PHY Timing" 



This reverts commit 417d8c47.

With that patch the panel in the Tentacruel ASUS Chromebook CM14
(CM1402F) flickers. There are 1 or 2 times per second a black panel.
Stable Kernel 6.11.5 and mainline 6.12-rc4 works only when reverse
that patch.

Fixes: 417d8c47 ("drm/mediatek: dsi: Correct calculation formula of PHY Timing")
Cc: stable@vger.kernel.org
Cc: Shuijing Li <shuijing.li@mediatek.com>
Reported-by: default avatarJens Ziller <zillerbaer@gmx.de>
Closes: https://patchwork.kernel.org/project/dri-devel/patch/20240412031208.30688-1-shuijing.li@mediatek.com/
Link: https://patchwork.kernel.org/project/dri-devel/patch/20241212001908.6056-1-chunkuang.hu@kernel.org/


Signed-off-by: default avatarChun-Kuang Hu <chunkuang.hu@kernel.org>
parent 40384c84

drivers/gpu/drm/mediatek/mtk_dsi.c

+15 −16
Original line number Diff line number Diff line
@@ -246,23 +246,22 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) 
	u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ);

	struct mtk_phy_timing *timing = &dsi->phy_timing;



	timing->lpx = (80 * data_rate_mhz / (8 * 1000)) + 1;

	timing->da_hs_prepare = (59 * data_rate_mhz + 4 * 1000) / 8000 + 1;

	timing->da_hs_zero = (163 * data_rate_mhz + 11 * 1000) / 8000 + 1 -

	timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;

	timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;

	timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -

			     timing->da_hs_prepare;

	timing->da_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 + 1;



	timing->ta_go = 4 * timing->lpx;

	timing->ta_sure = 3 * timing->lpx / 2;

	timing->ta_get = 5 * timing->lpx;

	timing->da_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1;



	timing->clk_hs_prepare = (57 * data_rate_mhz / (8 * 1000)) + 1;

	timing->clk_hs_post = (65 * data_rate_mhz + 53 * 1000) / 8000 + 1;

	timing->clk_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 + 1;

	timing->clk_hs_zero = (330 * data_rate_mhz / (8 * 1000)) + 1 -

			      timing->clk_hs_prepare;

	timing->clk_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1;

	timing->da_hs_trail = timing->da_hs_prepare + 1;



	timing->ta_go = 4 * timing->lpx - 2;

	timing->ta_sure = timing->lpx + 2;

	timing->ta_get = 4 * timing->lpx;

	timing->da_hs_exit = 2 * timing->lpx + 1;



	timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);

	timing->clk_hs_post = timing->clk_hs_prepare + 8;

	timing->clk_hs_trail = timing->clk_hs_prepare;

	timing->clk_hs_zero = timing->clk_hs_trail * 4;

	timing->clk_hs_exit = 2 * timing->clk_hs_trail;



	timcon0 = FIELD_PREP(LPX, timing->lpx) |

		  FIELD_PREP(HS_PREP, timing->da_hs_prepare) |