Commit d100de08 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/xilinx-xdma' 

- Move Xilinx IRQ definitions to a common header shared by pcie-xilinx-cpm
  and xilinx-xdma (Thippeswamy Havalige)

- Add Xilinx XDMA driver and DT schema (Thippeswamy Havalige)

* pci/controller/xilinx-xdma:
  PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver
  dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx XDMA PCIe Root Port Bridge
  PCI: xilinx-cpm: Move IRQ definitions to a common header
parents fb3d102f 8d786149

Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml

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+114 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Xilinx XDMA PL PCIe Root Port Bridge



maintainers:

  - Thippeswamy Havalige <thippeswamy.havalige@amd.com>



allOf:

  - $ref: /schemas/pci/pci-bus.yaml#



properties:

  compatible:

    const: xlnx,xdma-host-3.00



  reg:

    maxItems: 1



  ranges:

    maxItems: 2



  interrupts:

    items:

      - description: interrupt asserted when miscellaneous interrupt is received.

      - description: msi0 interrupt asserted when an MSI is received.

      - description: msi1 interrupt asserted when an MSI is received.



  interrupt-names:

    items:

      - const: misc

      - const: msi0

      - const: msi1



  interrupt-map-mask:

    items:

      - const: 0

      - const: 0

      - const: 0

      - const: 7



  interrupt-map:

    maxItems: 4



  "#interrupt-cells":

    const: 1



  interrupt-controller:

    description: identifies the node as an interrupt controller

    type: object

    properties:

      interrupt-controller: true



      "#address-cells":

        const: 0



      "#interrupt-cells":

        const: 1



    required:

      - interrupt-controller

      - "#address-cells"

      - "#interrupt-cells"



    additionalProperties: false



required:

  - compatible

  - reg

  - ranges

  - interrupts

  - interrupt-map

  - interrupt-map-mask

  - "#interrupt-cells"

  - interrupt-controller



unevaluatedProperties: false



examples:



  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;

        pcie@a0000000 {

            compatible = "xlnx,xdma-host-3.00";

            reg = <0x0 0xa0000000 0x0 0x10000000>;

            ranges = <0x2000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x1000000>,

                     <0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>;

            #address-cells = <3>;

            #size-cells = <2>;

            #interrupt-cells = <1>;

            device_type = "pci";

            interrupt-parent = <&gic>;

            interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "misc", "msi0", "msi1";

            interrupt-map-mask = <0x0 0x0 0x0 0x7>;

            interrupt-map = <0 0 0 1 &pcie_intc_0 0>,

                            <0 0 0 2 &pcie_intc_0 1>,

                            <0 0 0 3 &pcie_intc_0 2>,

                            <0 0 0 4 &pcie_intc_0 3>;

            pcie_intc_0: interrupt-controller {

                #address-cells = <0>;

                #interrupt-cells = <1>;

                interrupt-controller;

            };

        };

    };

drivers/pci/controller/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -324,6 +324,17 @@ config PCIE_XILINX 
	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe

	  Host Bridge driver.



config PCIE_XILINX_DMA_PL

	bool "Xilinx DMA PL PCIe host bridge support"

	depends on ARCH_ZYNQMP || COMPILE_TEST

	depends on PCI_MSI

	select PCI_HOST_COMMON

	help

	  Say 'Y' here if you want kernel support for the Xilinx PL DMA

	  PCIe host bridge. The controller is a Soft IP which can act as

	  Root Port. If your system provides Xilinx PCIe host controller

	  bridge DMA as Soft IP say 'Y'; if you are not sure, say 'N'.



config PCIE_XILINX_NWL

	bool "Xilinx NWL PCIe controller"

	depends on ARCH_ZYNQMP || COMPILE_TEST

drivers/pci/controller/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o 
obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o

obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o

obj-$(CONFIG_PCIE_XILINX_CPM) += pcie-xilinx-cpm.o

obj-$(CONFIG_PCIE_XILINX_DMA_PL) += pcie-xilinx-dma-pl.o

obj-$(CONFIG_PCI_V3_SEMI) += pci-v3-semi.o

obj-$(CONFIG_PCI_XGENE) += pci-xgene.o

obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o

drivers/pci/controller/pcie-xilinx-common.h

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+31 −0
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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * (C) Copyright 2023, Xilinx, Inc.

 */



#include <linux/pci.h>

#include <linux/pci-ecam.h>

#include <linux/platform_device.h>



/* Interrupt registers definitions */

#define XILINX_PCIE_INTR_LINK_DOWN		0

#define XILINX_PCIE_INTR_HOT_RESET		3

#define XILINX_PCIE_INTR_CFG_PCIE_TIMEOUT	4

#define XILINX_PCIE_INTR_CFG_TIMEOUT		8

#define XILINX_PCIE_INTR_CORRECTABLE		9

#define XILINX_PCIE_INTR_NONFATAL		10

#define XILINX_PCIE_INTR_FATAL			11

#define XILINX_PCIE_INTR_CFG_ERR_POISON		12

#define XILINX_PCIE_INTR_PME_TO_ACK_RCVD	15

#define XILINX_PCIE_INTR_INTX			16

#define XILINX_PCIE_INTR_PM_PME_RCVD		17

#define XILINX_PCIE_INTR_MSI			17

#define XILINX_PCIE_INTR_SLV_UNSUPP		20

#define XILINX_PCIE_INTR_SLV_UNEXP		21

#define XILINX_PCIE_INTR_SLV_COMPL		22

#define XILINX_PCIE_INTR_SLV_ERRP		23

#define XILINX_PCIE_INTR_SLV_CMPABT		24

#define XILINX_PCIE_INTR_SLV_ILLBUR		25

#define XILINX_PCIE_INTR_MST_DECERR		26

#define XILINX_PCIE_INTR_MST_SLVERR		27

#define XILINX_PCIE_INTR_SLV_PCIE_TIMEOUT	28

drivers/pci/controller/pcie-xilinx-cpm.c

+7 −31
Original line number Diff line number Diff line
@@ -16,11 +16,9 @@ 
#include <linux/of_address.h>

#include <linux/of_pci.h>

#include <linux/of_platform.h>

#include <linux/pci.h>

#include <linux/platform_device.h>

#include <linux/pci-ecam.h>



#include "../pci.h"

#include "pcie-xilinx-common.h"



/* Register definitions */

#define XILINX_CPM_PCIE_REG_IDR		0x00000E10
@@ -38,29 +36,7 @@ 
#define XILINX_CPM_PCIE_IR_ENABLE       0x000002A8

#define XILINX_CPM_PCIE_IR_LOCAL        BIT(0)



/* Interrupt registers definitions */

#define XILINX_CPM_PCIE_INTR_LINK_DOWN		0

#define XILINX_CPM_PCIE_INTR_HOT_RESET		3

#define XILINX_CPM_PCIE_INTR_CFG_PCIE_TIMEOUT	4

#define XILINX_CPM_PCIE_INTR_CFG_TIMEOUT	8

#define XILINX_CPM_PCIE_INTR_CORRECTABLE	9

#define XILINX_CPM_PCIE_INTR_NONFATAL		10

#define XILINX_CPM_PCIE_INTR_FATAL		11

#define XILINX_CPM_PCIE_INTR_CFG_ERR_POISON	12

#define XILINX_CPM_PCIE_INTR_PME_TO_ACK_RCVD	15

#define XILINX_CPM_PCIE_INTR_INTX		16

#define XILINX_CPM_PCIE_INTR_PM_PME_RCVD	17

#define XILINX_CPM_PCIE_INTR_SLV_UNSUPP		20

#define XILINX_CPM_PCIE_INTR_SLV_UNEXP		21

#define XILINX_CPM_PCIE_INTR_SLV_COMPL		22

#define XILINX_CPM_PCIE_INTR_SLV_ERRP		23

#define XILINX_CPM_PCIE_INTR_SLV_CMPABT		24

#define XILINX_CPM_PCIE_INTR_SLV_ILLBUR		25

#define XILINX_CPM_PCIE_INTR_MST_DECERR		26

#define XILINX_CPM_PCIE_INTR_MST_SLVERR		27

#define XILINX_CPM_PCIE_INTR_SLV_PCIE_TIMEOUT	28



#define IMR(x) BIT(XILINX_CPM_PCIE_INTR_ ##x)

#define IMR(x) BIT(XILINX_PCIE_INTR_ ##x)



#define XILINX_CPM_PCIE_IMR_ALL_MASK			\

	(						\
@@ -323,7 +299,7 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc) 
}



#define _IC(x, s)                              \

	[XILINX_CPM_PCIE_INTR_ ## x] = { __stringify(x), s }

	[XILINX_PCIE_INTR_ ## x] = { __stringify(x), s }



static const struct {

	const char      *sym;
@@ -359,9 +335,9 @@ static irqreturn_t xilinx_cpm_pcie_intr_handler(int irq, void *dev_id) 
	d = irq_domain_get_irq_data(port->cpm_domain, irq);



	switch (d->hwirq) {

	case XILINX_CPM_PCIE_INTR_CORRECTABLE:

	case XILINX_CPM_PCIE_INTR_NONFATAL:

	case XILINX_CPM_PCIE_INTR_FATAL:

	case XILINX_PCIE_INTR_CORRECTABLE:

	case XILINX_PCIE_INTR_NONFATAL:

	case XILINX_PCIE_INTR_FATAL:

		cpm_pcie_clear_err_interrupts(port);

		fallthrough;
@@ -466,7 +442,7 @@ static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie *port) 
	}



	port->intx_irq = irq_create_mapping(port->cpm_domain,

					    XILINX_CPM_PCIE_INTR_INTX);

					    XILINX_PCIE_INTR_INTX);

	if (!port->intx_irq) {

		dev_err(dev, "Failed to map INTx interrupt\n");

		return -ENXIO;