Commit d15cbe71 authored by Bharat Bhushan's avatar Bharat Bhushan Committed by Herbert Xu
Browse files

crypto: octeontx2 - Use dynamic allocated memory region for lmtst 



Current driver uses static LMTST region allocated by firmware.
Firmware allocated memory for LMTST is available in PF/VF BAR2.
Using this memory have performance impact as this is mapped as
device memory. There is another option to allocate contiguous
memory at run time and map this in LMT MAP table with the
help of AF driver. With this patch dynamic allocated memory
is used for LMTST.

Also add myself as maintainer for crypto octeontx2 driver

Signed-off-by: default avatarBharat Bhushan <bbhushan2@marvell.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 57b1e1c0

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -14290,6 +14290,7 @@ F: include/uapi/drm/armada_drm.h 








MARVELL CRYPTO DRIVER









M:	Srujana Challa <schalla@marvell.com>









M:	Bharat Bhushan <bbhushan2@marvell.com>









L:	linux-crypto@vger.kernel.org









S:	Maintained









F:	drivers/crypto/marvell/
































drivers/crypto/marvell/octeontx2/cn10k_cpt.c



+66
−23






























Original line number
Diff line number
Diff line







@@ -6,6 +6,7 @@







#include "otx2_cptvf.h"









#include "otx2_cptlf.h"









#include "cn10k_cpt.h"









#include "otx2_cpt_common.h"



















static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,









			       struct otx2_cptlf_info *lf);








@@ -27,7 +28,7 @@ static struct cpt_hw_ops cn10k_hw_ops = {







static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,









			       struct otx2_cptlf_info *lf)









{









	void __iomem *lmtline = lf->lmtline;









	void *lmtline = lf->lfs->lmt_info.base + (lf->slot * LMTLINE_SIZE);









	u64 val = (lf->slot & 0x7FF);









	u64 tar_addr = 0;


















@@ -41,15 +42,49 @@ static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,







	dma_wmb();



















	/* Copy CPT command to LMTLINE */









	memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE);









	memcpy(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE);









	cn10k_lmt_flush(val, tar_addr);









}



















void cn10k_cpt_lmtst_free(struct pci_dev *pdev, struct otx2_cptlfs_info *lfs)









{









	struct otx2_lmt_info *lmt_info = &lfs->lmt_info;



















	if (!lmt_info->base)









		return;



















	dma_free_attrs(&pdev->dev, lmt_info->size,









		       lmt_info->base - lmt_info->align,









		       lmt_info->iova - lmt_info->align,









		       DMA_ATTR_FORCE_CONTIGUOUS);









}









EXPORT_SYMBOL_NS_GPL(cn10k_cpt_lmtst_free, "CRYPTO_DEV_OCTEONTX2_CPT");



















static int cn10k_cpt_lmtst_alloc(struct pci_dev *pdev,









				 struct otx2_cptlfs_info *lfs, u32 size)









{









	struct otx2_lmt_info *lmt_info = &lfs->lmt_info;









	dma_addr_t align_iova;









	dma_addr_t iova;



















	lmt_info->base = dma_alloc_attrs(&pdev->dev, size, &iova, GFP_KERNEL,









					 DMA_ATTR_FORCE_CONTIGUOUS);









	if (!lmt_info->base)









		return -ENOMEM;



















	align_iova = ALIGN((u64)iova, LMTLINE_ALIGN);









	lmt_info->iova = align_iova;









	lmt_info->align = align_iova - iova;









	lmt_info->size = size;









	lmt_info->base += lmt_info->align;









	return 0;









}



















int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf)









{









	struct pci_dev *pdev = cptpf->pdev;









	resource_size_t size;









	u64 lmt_base;









	u32 size;









	int ret;



















	if (!test_bit(CN10K_LMTST, &cptpf->cap_flag)) {









		cptpf->lfs.ops = &otx2_hw_ops;








@@ -57,18 +92,19 @@ int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf)







	}



















	cptpf->lfs.ops = &cn10k_hw_ops;









	lmt_base = readq(cptpf->reg_base + RVU_PF_LMTLINE_ADDR);









	if (!lmt_base) {









		dev_err(&pdev->dev, "PF LMTLINE address not configured\n");









		return -ENOMEM;









	size = OTX2_CPT_MAX_VFS_NUM * LMTLINE_SIZE + LMTLINE_ALIGN;









	ret = cn10k_cpt_lmtst_alloc(pdev, &cptpf->lfs, size);









	if (ret) {









		dev_err(&pdev->dev, "PF-%d LMTLINE memory allocation failed\n",









			cptpf->pf_id);









		return ret;









	}









	size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);









	size -= ((1 + cptpf->max_vfs) * MBOX_SIZE);









	cptpf->lfs.lmt_base = devm_ioremap_wc(&pdev->dev, lmt_base, size);









	if (!cptpf->lfs.lmt_base) {









		dev_err(&pdev->dev,









			"Mapping of PF LMTLINE address failed\n");









		return -ENOMEM;



















	ret = otx2_cpt_lmtst_tbl_setup_msg(&cptpf->lfs);









	if (ret) {









		dev_err(&pdev->dev, "PF-%d: LMTST Table setup failed\n",









		cptpf->pf_id);









		cn10k_cpt_lmtst_free(pdev, &cptpf->lfs);









	}



















	return 0;








@@ -78,18 +114,25 @@ EXPORT_SYMBOL_NS_GPL(cn10k_cptpf_lmtst_init, "CRYPTO_DEV_OCTEONTX2_CPT");







int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf)









{









	struct pci_dev *pdev = cptvf->pdev;









	resource_size_t offset, size;









	u32 size;









	int ret;



















	if (!test_bit(CN10K_LMTST, &cptvf->cap_flag))









		return 0;



















	offset = pci_resource_start(pdev, PCI_MBOX_BAR_NUM);









	size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);









	/* Map VF LMILINE region */









	cptvf->lfs.lmt_base = devm_ioremap_wc(&pdev->dev, offset, size);









	if (!cptvf->lfs.lmt_base) {









		dev_err(&pdev->dev, "Unable to map BAR4\n");









		return -ENOMEM;









	size = cptvf->lfs.lfs_num * LMTLINE_SIZE + LMTLINE_ALIGN;









	ret = cn10k_cpt_lmtst_alloc(pdev, &cptvf->lfs, size);









	if (ret) {









		dev_err(&pdev->dev, "VF-%d LMTLINE memory allocation failed\n",









			cptvf->vf_id);









		return ret;









	}



















	ret = otx2_cpt_lmtst_tbl_setup_msg(&cptvf->lfs);









	if (ret) {









		dev_err(&pdev->dev, "VF-%d: LMTST Table setup failed\n",









			cptvf->vf_id);









		cn10k_cpt_lmtst_free(pdev, &cptvf->lfs);









	}



















	return 0;
































drivers/crypto/marvell/octeontx2/cn10k_cpt.h



+1
−0






























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@@ -50,6 +50,7 @@ static inline u8 otx2_cpt_get_uc_compcode(union otx2_cpt_res_s *result)

















int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf);









int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf);









void cn10k_cpt_lmtst_free(struct pci_dev *pdev, struct otx2_cptlfs_info *lfs);









void cn10k_cpt_ctx_flush(struct pci_dev *pdev, u64 cptr, bool inval);









int cn10k_cpt_hw_ctx_init(struct pci_dev *pdev,









			  struct cn10k_cpt_errata_ctx *er_ctx);
































drivers/crypto/marvell/octeontx2/otx2_cpt_common.h



+1
−0






























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@@ -209,5 +209,6 @@ int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs);







int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs);









int otx2_cpt_sync_mbox_msg(struct otx2_mbox *mbox);









int otx2_cpt_lf_reset_msg(struct otx2_cptlfs_info *lfs, int slot);









int otx2_cpt_lmtst_tbl_setup_msg(struct otx2_cptlfs_info *lfs);



















#endif /* __OTX2_CPT_COMMON_H */
























drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c



+25
−0






























Original line number
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@@ -255,3 +255,28 @@ int otx2_cpt_lf_reset_msg(struct otx2_cptlfs_info *lfs, int slot)







	return ret;









}









EXPORT_SYMBOL_NS_GPL(otx2_cpt_lf_reset_msg, "CRYPTO_DEV_OCTEONTX2_CPT");



















int otx2_cpt_lmtst_tbl_setup_msg(struct otx2_cptlfs_info *lfs)









{









	struct otx2_mbox *mbox = lfs->mbox;









	struct pci_dev *pdev = lfs->pdev;









	struct lmtst_tbl_setup_req *req;



















	req = (struct lmtst_tbl_setup_req *)









	       otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),









				       sizeof(struct msg_rsp));









	if (!req) {









		dev_err(&pdev->dev, "RVU MBOX failed to alloc message.\n");









		return -EFAULT;









	}



















	req->hdr.id = MBOX_MSG_LMTST_TBL_SETUP;









	req->hdr.sig = OTX2_MBOX_REQ_SIG;









	req->hdr.pcifunc = 0;



















	req->use_local_lmt_region = true;









	req->lmt_iova = lfs->lmt_info.iova;



















	return otx2_cpt_send_mbox_msg(mbox, pdev);









}









EXPORT_SYMBOL_NS_GPL(otx2_cpt_lmtst_tbl_setup_msg, "CRYPTO_DEV_OCTEONTX2_CPT");