Commit d1a7be73 authored by Rob Herring (Arm)'s avatar Rob Herring (Arm)
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dt-bindings: gpu: Convert nvidia,gk20a to DT schema 



Convert the NVIDIA GPU binding to DT schema format.

Add undocumented "interconnects" and "interconnect-names" properties for
gp10b and gv11b. Drop all but one example.

Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
parent 532a9435

Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt

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NVIDIA Tegra Graphics Processing Units



Required properties:

- compatible: "nvidia,<gpu>"

  Currently recognized values:

  - nvidia,gk20a

  - nvidia,gm20b

  - nvidia,gp10b

  - nvidia,gv11b

- reg: Physical base address and length of the controller's registers.

  Must contain two entries:

  - first entry for bar0

  - second entry for bar1

- interrupts: Must contain an entry for each entry in interrupt-names.

  See ../interrupt-controller/interrupts.txt for details.

- interrupt-names: Must include the following entries:

  - stall

  - nonstall

- vdd-supply: regulator for supply voltage. Only required for GPUs not using

  power domains.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - gpu

  - pwr

If the compatible string is "nvidia,gm20b", then the following clock

is also required:

  - ref

If the compatible string is "nvidia,gv11b", then the following clock is also

required:

  - fuse

- resets: Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names: Must include the following entries:

  - gpu

- power-domains: GPUs that make use of power domains can define this property

  instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.



Optional properties:

- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.



Example for GK20A:



	gpu@57000000 {

		compatible = "nvidia,gk20a";

		reg = <0x0 0x57000000 0x0 0x01000000>,

		      <0x0 0x58000000 0x0 0x01000000>;

		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "stall", "nonstall";

		vdd-supply = <&vdd_gpu>;

		clocks = <&tegra_car TEGRA124_CLK_GPU>,

			 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;

		clock-names = "gpu", "pwr";

		resets = <&tegra_car 184>;

		reset-names = "gpu";

		iommus = <&mc TEGRA_SWGROUP_GPU>;

	};



Example for GM20B:



	gpu@57000000 {

		compatible = "nvidia,gm20b";

		reg = <0x0 0x57000000 0x0 0x01000000>,

		      <0x0 0x58000000 0x0 0x01000000>;

		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "stall", "nonstall";

		clocks = <&tegra_car TEGRA210_CLK_GPU>,

			 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,

			 <&tegra_car TEGRA210_CLK_PLL_G_REF>;

		clock-names = "gpu", "pwr", "ref";

		resets = <&tegra_car 184>;

		reset-names = "gpu";

		iommus = <&mc TEGRA_SWGROUP_GPU>;

	};



Example for GP10B:



	gpu@17000000 {

		compatible = "nvidia,gp10b";

		reg = <0x0 0x17000000 0x0 0x1000000>,

		      <0x0 0x18000000 0x0 0x1000000>;

		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH

			      GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "stall", "nonstall";

		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,

			 <&bpmp TEGRA186_CLK_GPU>;

		clock-names = "gpu", "pwr";

		resets = <&bpmp TEGRA186_RESET_GPU>;

		reset-names = "gpu";

		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;

		iommus = <&smmu TEGRA186_SID_GPU>;

	};



Example for GV11B:



	gpu@17000000 {

		compatible = "nvidia,gv11b";

		reg = <0x17000000 0x1000000>,

		      <0x18000000 0x1000000>;

		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "stall", "nonstall";

		clocks = <&bpmp TEGRA194_CLK_GPCCLK>,

			 <&bpmp TEGRA194_CLK_GPU_PWR>,

			 <&bpmp TEGRA194_CLK_FUSE>;

		clock-names = "gpu", "pwr", "fuse";

		resets = <&bpmp TEGRA194_RESET_GPU>;

		reset-names = "gpu";

		dma-coherent;



		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;

		iommus = <&smmu TEGRA194_SID_GPU>;

	};

Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/gpu/nvidia,gk20a.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NVIDIA Tegra Graphics Processing Units



maintainers:

  - Alexandre Courbot <acourbot@nvidia.com>

  - Jon Hunter <jonathanh@nvidia.com>

  - Thierry Reding <treding@nvidia.com>



properties:

  compatible:

    enum:

      - nvidia,gk20a

      - nvidia,gm20b

      - nvidia,gp10b

      - nvidia,gv11b



  reg:

    items:

      - description: Bar0 register window

      - description: Bar1 register window



  interrupts:

    items:

      - description: Stall interrupt

      - description: Nonstall interrupt



  interrupt-names:

    items:

      - const: stall

      - const: nonstall



  vdd-supply:

    description:

      Regulator for GPU supply voltage



  clocks:

    minItems: 2

    items:

      - description: GPU clock

      - description: Power clock

      - description: Reference or fuse clock



  clock-names:

    minItems: 2

    items:

      - const: gpu

      - const: pwr

      - enum: [ ref, fuse ]



  resets:

    maxItems: 1



  reset-names:

    items:

      - const: gpu



  power-domains:

    maxItems: 1



  interconnects:

    minItems: 4

    maxItems: 12



  interconnect-names:

    minItems: 4

    maxItems: 12



  iommus:

    maxItems: 1



  dma-coherent: true



required:

  - compatible

  - reg

  - interrupts

  - interrupt-names

  - clocks

  - clock-names

  - resets

  - reset-names



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - nvidia,gp10b

              - nvidia,gv11b

    then:

      required:

        - power-domains

    else:

      properties:

        interconnects: false

        interconnect-names: false



      required:

        - vdd-supply

  - if:

      properties:

        compatible:

          contains:

            enum:

              - nvidia,gp10b

    then:

      properties:

        interconnects:

          maxItems: 4



        interconnect-names:

          items:

            - const: dma-mem

            - const: write-0

            - const: read-1

            - const: write-1

  - if:

      properties:

        compatible:

          contains:

            enum:

              - nvidia,gv11b

    then:

      properties:

        interconnects:

          minItems: 12



        interconnect-names:

          items:

            - const: dma-mem

            - const: read-0-hp

            - const: write-0

            - const: read-1

            - const: read-1-hp

            - const: write-1

            - const: read-2

            - const: read-2-hp

            - const: write-2

            - const: read-3

            - const: read-3-hp

            - const: write-3



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/tegra124-car-common.h>

    #include <dt-bindings/memory/tegra124-mc.h>



    gpu@57000000 {

        compatible = "nvidia,gk20a";

        reg = <0x57000000 0x01000000>,

              <0x58000000 0x01000000>;

        interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-names = "stall", "nonstall";

        vdd-supply = <&vdd_gpu>;

        clocks = <&tegra_car TEGRA124_CLK_GPU>,

                 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;

        clock-names = "gpu", "pwr";

        resets = <&tegra_car 184>;

        reset-names = "gpu";

        iommus = <&mc TEGRA_SWGROUP_GPU>;

    };