Commit d1cf738f authored by Serge Semin's avatar Serge Semin Committed by Bjorn Helgaas
Browse files

PCI: dwc: Add unroll iATU space support to dw_pcie_disable_atu() 

dw_pcie_disable_atu() was introduced by f8aed6ec ("PCI: dwc:
designware: Add EP mode support") and supported only the viewport version
of the iATU CSRs.

DW PCIe IP cores v4.80a and newer also support unrolled iATU/eDMA space.
Callers of dw_pcie_disable_atu(), including pci_epc_ops.clear_bar(),
pci_epc_ops.unmap_addr(), and dw_pcie_setup_rc(), don't work correctly when
it is enabled.

Add dw_pcie_disable_atu() support for controllers with unrolled iATU CSRs
enabled.

[bhelgaas: commit log]
Fixes: f8aed6ec ("PCI: dwc: designware: Add EP mode support")
Link: https://lore.kernel.org/r/20220624143428.8334-3-Sergey.Semin@baikalelectronics.ru


Tested-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
parent 113fa857

drivers/pci/controller/dwc/pcie-designware.c

+13 −3
Original line number Diff line number Diff line
@@ -491,7 +491,7 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, 
void dw_pcie_disable_atu(struct dw_pcie *pci, int index,

			 enum dw_pcie_region_type type)

{

	int region;

	u32 region;



	switch (type) {

	case DW_PCIE_REGION_INBOUND:
@@ -504,9 +504,19 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, int index, 
		return;

	}



	if (pci->iatu_unroll_enabled) {

		if (region == PCIE_ATU_REGION_INBOUND) {

			dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,

						 ~(u32)PCIE_ATU_ENABLE);

		} else {

			dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,

						 ~(u32)PCIE_ATU_ENABLE);

		}

	} else {

		dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);

		dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE);

	}

}



int dw_pcie_wait_for_link(struct dw_pcie *pci)

{