Commit d2f59bf9 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'net-stmmac-cleanups-and-low-priority-fixes' 

Russell King says:

====================
net: stmmac: cleanups and low priority fixes

Further cleanups and a few low priority fixes:

- Remove duplicated register definitions from header files
- Fix harmless wrong definition used for PTP message type in
  descriptors
- Fix norm_set_tx_desc_len_on_ring() off-by-one error (and make
  enh_set_tx_desc_len_on_ring() follow a similar pattern.)
  Document the buffer size limits. I believe we never call
  norm_set_tx_desc_len_on_ring() with 2KiB lengths.
- use u32 rather than unsigned int for 32-bit quantities in
  descriptors
- modernise: convert to use FIELD_PREP() rather than separate mask
  and shift definitions.
- Reorganise register and register field definitions: registers
  defined in address offset order followed by their register field
  definitions.
- Remove lots of unused register definitions.
====================

Link: https://patch.msgid.link/aV_q2Kneinrk3Z-W@shell.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 5c024716 5a78fd3d

drivers/net/ethernet/stmicro/stmmac/descs.h

+0 −7
Original line number Diff line number Diff line
@@ -32,13 +32,11 @@ 
#define	RDES0_DESCRIPTOR_ERROR	BIT(14)

#define	RDES0_ERROR_SUMMARY	BIT(15)

#define	RDES0_FRAME_LEN_MASK	GENMASK(29, 16)

#define RDES0_FRAME_LEN_SHIFT	16

#define	RDES0_DA_FILTER_FAIL	BIT(30)

#define	RDES0_OWN		BIT(31)

			/* RDES1 */

#define	RDES1_BUFFER1_SIZE_MASK		GENMASK(10, 0)

#define	RDES1_BUFFER2_SIZE_MASK		GENMASK(21, 11)

#define	RDES1_BUFFER2_SIZE_SHIFT	11

#define	RDES1_SECOND_ADDRESS_CHAINED	BIT(24)

#define	RDES1_END_RING			BIT(25)

#define	RDES1_DISABLE_IC		BIT(31)
@@ -53,7 +51,6 @@ 
#define	ERDES1_SECOND_ADDRESS_CHAINED	BIT(14)

#define	ERDES1_END_RING			BIT(15)

#define	ERDES1_BUFFER2_SIZE_MASK	GENMASK(28, 16)

#define ERDES1_BUFFER2_SIZE_SHIFT	16

#define	ERDES1_DISABLE_IC		BIT(31)



/* Normal transmit descriptor defines */
@@ -77,14 +74,12 @@ 
/* TDES1 */

#define	TDES1_BUFFER1_SIZE_MASK		GENMASK(10, 0)

#define	TDES1_BUFFER2_SIZE_MASK		GENMASK(21, 11)

#define	TDES1_BUFFER2_SIZE_SHIFT	11

#define	TDES1_TIME_STAMP_ENABLE		BIT(22)

#define	TDES1_DISABLE_PADDING		BIT(23)

#define	TDES1_SECOND_ADDRESS_CHAINED	BIT(24)

#define	TDES1_END_RING			BIT(25)

#define	TDES1_CRC_DISABLE		BIT(26)

#define	TDES1_CHECKSUM_INSERTION_MASK	GENMASK(28, 27)

#define	TDES1_CHECKSUM_INSERTION_SHIFT	27

#define	TDES1_FIRST_SEGMENT		BIT(29)

#define	TDES1_LAST_SEGMENT		BIT(30)

#define	TDES1_INTERRUPT			BIT(31)
@@ -109,7 +104,6 @@ 
#define	ETDES0_SECOND_ADDRESS_CHAINED	BIT(20)

#define	ETDES0_END_RING			BIT(21)

#define	ETDES0_CHECKSUM_INSERTION_MASK	GENMASK(23, 22)

#define	ETDES0_CHECKSUM_INSERTION_SHIFT	22

#define	ETDES0_TIME_STAMP_ENABLE	BIT(25)

#define	ETDES0_DISABLE_PADDING		BIT(26)

#define	ETDES0_CRC_DISABLE		BIT(27)
@@ -120,7 +114,6 @@ 
/* TDES1 */

#define	ETDES1_BUFFER1_SIZE_MASK	GENMASK(12, 0)

#define	ETDES1_BUFFER2_SIZE_MASK	GENMASK(28, 16)

#define	ETDES1_BUFFER2_SIZE_SHIFT	16



/* Extended Receive descriptor definitions */

#define	ERDES4_IP_PAYLOAD_TYPE_MASK	GENMASK(6, 2)

drivers/net/ethernet/stmicro/stmmac/descs_com.h

+28 −20
Original line number Diff line number Diff line
@@ -23,9 +23,8 @@ static inline void ehn_desc_rx_set_on_ring(struct dma_desc *p, int end, 
					   int bfsize)

{

	if (bfsize == BUF_SIZE_16KiB)

		p->des1 |= cpu_to_le32((BUF_SIZE_8KiB

				<< ERDES1_BUFFER2_SIZE_SHIFT)

			   & ERDES1_BUFFER2_SIZE_MASK);

		p->des1 |= cpu_to_le32(FIELD_PREP(ERDES1_BUFFER2_SIZE_MASK,

						  BUF_SIZE_8KiB));



	if (end)

		p->des1 |= cpu_to_le32(ERDES1_END_RING);
@@ -39,15 +38,20 @@ static inline void enh_desc_end_tx_desc_on_ring(struct dma_desc *p, int end) 
		p->des0 &= cpu_to_le32(~ETDES0_END_RING);

}



/* The maximum buffer 1 size is 8KiB - 1. However, we limit to 4KiB. */

static inline void enh_set_tx_desc_len_on_ring(struct dma_desc *p, int len)

{

	if (unlikely(len > BUF_SIZE_4KiB)) {

		p->des1 |= cpu_to_le32((((len - BUF_SIZE_4KiB)

					<< ETDES1_BUFFER2_SIZE_SHIFT)

			    & ETDES1_BUFFER2_SIZE_MASK) | (BUF_SIZE_4KiB

			    & ETDES1_BUFFER1_SIZE_MASK));

	} else

		p->des1 |= cpu_to_le32((len & ETDES1_BUFFER1_SIZE_MASK));

	unsigned int buffer1_max_length = BUF_SIZE_4KiB;



	if (unlikely(len > buffer1_max_length)) {

		p->des1 |= cpu_to_le32(FIELD_PREP(ETDES1_BUFFER2_SIZE_MASK,

						  len - buffer1_max_length) |

				       FIELD_PREP(ETDES1_BUFFER1_SIZE_MASK,

						  buffer1_max_length));

	} else {

		p->des1 |= cpu_to_le32(FIELD_PREP(ETDES1_BUFFER1_SIZE_MASK,

						  len));

	}

}



/* Normal descriptors */
@@ -57,8 +61,8 @@ static inline void ndesc_rx_set_on_ring(struct dma_desc *p, int end, int bfsize) 
		int bfsize2;



		bfsize2 = min(bfsize - BUF_SIZE_2KiB + 1, BUF_SIZE_2KiB - 1);

		p->des1 |= cpu_to_le32((bfsize2 << RDES1_BUFFER2_SIZE_SHIFT)

			    & RDES1_BUFFER2_SIZE_MASK);

		p->des1 |= cpu_to_le32(FIELD_PREP(RDES1_BUFFER2_SIZE_MASK,

						  bfsize2));

	}



	if (end)
@@ -73,16 +77,20 @@ static inline void ndesc_end_tx_desc_on_ring(struct dma_desc *p, int end) 
		p->des1 &= cpu_to_le32(~TDES1_END_RING);

}



/* The maximum buffer 1 size is 2KiB - 1, limited by the mask width */

static inline void norm_set_tx_desc_len_on_ring(struct dma_desc *p, int len)

{

	if (unlikely(len > BUF_SIZE_2KiB)) {

		unsigned int buffer1 = (BUF_SIZE_2KiB - 1)

					& TDES1_BUFFER1_SIZE_MASK;

		p->des1 |= cpu_to_le32((((len - buffer1)

					<< TDES1_BUFFER2_SIZE_SHIFT)

				& TDES1_BUFFER2_SIZE_MASK) | buffer1);

	} else

		p->des1 |= cpu_to_le32((len & TDES1_BUFFER1_SIZE_MASK));

	unsigned int buffer1_max_length = BUF_SIZE_2KiB - 1;



	if (unlikely(len > buffer1_max_length)) {

		p->des1 |= cpu_to_le32(FIELD_PREP(TDES1_BUFFER2_SIZE_MASK,

						  len - buffer1_max_length) |

				       FIELD_PREP(TDES1_BUFFER1_SIZE_MASK,

						  buffer1_max_length));

	} else {

		p->des1 |= cpu_to_le32(FIELD_PREP(TDES1_BUFFER1_SIZE_MASK,

						  len));

	}

}



/* Specific functions used for Chain mode */

drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c

+2 −3
Original line number Diff line number Diff line
@@ -192,9 +192,8 @@ static void loongson_dwmac_dma_init_channel(struct stmmac_priv *priv, 
		value |= DMA_BUS_MODE_MAXPBL;



	value |= DMA_BUS_MODE_USP;

	value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK);

	value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT);

	value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);

	value = u32_replace_bits(value, txpbl, DMA_BUS_MODE_PBL_MASK);

	value = u32_replace_bits(value, rxpbl, DMA_BUS_MODE_RPBL_MASK);



	/* Set the Fixed burst mode */

	if (dma_cfg->fixed_burst)

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

+2 −3
Original line number Diff line number Diff line
@@ -367,9 +367,8 @@ static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *system, 
		.use_nsecs = false,

	};



	num_snapshot = (readl(ioaddr + XGMAC_TIMESTAMP_STATUS) &

			XGMAC_TIMESTAMP_ATSNS_MASK) >>

			XGMAC_TIMESTAMP_ATSNS_SHIFT;

	num_snapshot = FIELD_GET(XGMAC_TIMESTAMP_ATSNS_MASK,

				 readl(ioaddr + XGMAC_TIMESTAMP_STATUS));



	/* Repeat until the timestamps are from the FIFO last segment */

	for (i = 0; i < num_snapshot; i++) {

drivers/net/ethernet/stmicro/stmmac/dwmac100.h

+2 −34
Original line number Diff line number Diff line
@@ -30,62 +30,30 @@ 
#define MAC_VLAN2	0x00000024	/* VLAN2 Tag */



/* MAC CTRL defines */

#define MAC_CONTROL_RA	0x80000000	/* Receive All Mode */

#define MAC_CONTROL_BLE	0x40000000	/* Endian Mode */

#define MAC_CONTROL_HBD	0x10000000	/* Heartbeat Disable */

#define MAC_CONTROL_PS	0x08000000	/* Port Select */

#define MAC_CONTROL_DRO	0x00800000	/* Disable Receive Own */

#define MAC_CONTROL_EXT_LOOPBACK 0x00400000	/* Reserved (ext loopback?) */

#define MAC_CONTROL_OM	0x00200000	/* Loopback Operating Mode */

#define MAC_CONTROL_F	0x00100000	/* Full Duplex Mode */

#define MAC_CONTROL_PM	0x00080000	/* Pass All Multicast */

#define MAC_CONTROL_PR	0x00040000	/* Promiscuous Mode */

#define MAC_CONTROL_IF	0x00020000	/* Inverse Filtering */

#define MAC_CONTROL_PB	0x00010000	/* Pass Bad Frames */

#define MAC_CONTROL_HO	0x00008000	/* Hash Only Filtering Mode */

#define MAC_CONTROL_HP	0x00002000	/* Hash/Perfect Filtering Mode */

#define MAC_CONTROL_LCC	0x00001000	/* Late Collision Control */

#define MAC_CONTROL_DBF	0x00000800	/* Disable Broadcast Frames */

#define MAC_CONTROL_DRTY	0x00000400	/* Disable Retry */

#define MAC_CONTROL_ASTP	0x00000100	/* Automatic Pad Stripping */

#define MAC_CONTROL_BOLMT_10	0x00000000	/* Back Off Limit 10 */

#define MAC_CONTROL_BOLMT_8	0x00000040	/* Back Off Limit 8 */

#define MAC_CONTROL_BOLMT_4	0x00000080	/* Back Off Limit 4 */

#define MAC_CONTROL_BOLMT_1	0x000000c0	/* Back Off Limit 1 */

#define MAC_CONTROL_DC		0x00000020	/* Deferral Check */

#define MAC_CONTROL_TE		0x00000008	/* Transmitter Enable */

#define MAC_CONTROL_RE		0x00000004	/* Receiver Enable */



#define MAC_CORE_INIT (MAC_CONTROL_HBD)



/* MAC FLOW CTRL defines */

#define MAC_FLOW_CTRL_PT_MASK	0xffff0000	/* Pause Time Mask */

#define MAC_FLOW_CTRL_PT_SHIFT	16

#define MAC_FLOW_CTRL_PASS	0x00000004	/* Pass Control Frames */

#define MAC_FLOW_CTRL_PT_MASK	GENMASK(31, 16)	/* Pause Time Mask */

#define MAC_FLOW_CTRL_ENABLE	0x00000002	/* Flow Control Enable */

#define MAC_FLOW_CTRL_PAUSE	0x00000001	/* Flow Control Busy ... */



/* MII ADDR  defines */

#define MAC_MII_ADDR_WRITE	0x00000002	/* MII Write */

#define MAC_MII_ADDR_BUSY	0x00000001	/* MII Busy */



/*----------------------------------------------------------------------------

 * 				DMA BLOCK defines

 *---------------------------------------------------------------------------*/



/* DMA Bus Mode register defines */

#define DMA_BUS_MODE_DBO	0x00100000	/* Descriptor Byte Ordering */

#define DMA_BUS_MODE_BLE	0x00000080	/* Big Endian/Little Endian */

#define DMA_BUS_MODE_PBL_MASK	0x00003f00	/* Programmable Burst Len */

#define DMA_BUS_MODE_PBL_SHIFT	8

#define DMA_BUS_MODE_DSL_MASK	0x0000007c	/* Descriptor Skip Length */

#define DMA_BUS_MODE_DSL_SHIFT	2	/*   (in DWORDS)      */

#define DMA_BUS_MODE_BAR_BUS	0x00000002	/* Bar-Bus Arbitration */

#define DMA_BUS_MODE_PBL_MASK	GENMASK(13, 8)	/* Programmable Burst Len */

#define DMA_BUS_MODE_DEFAULT	0x00000000



/* DMA Control register defines */

#define DMA_CONTROL_SF		0x00200000	/* Store And Forward */



/* Transmit Threshold Control */

enum ttc_control {

	DMA_CONTROL_TTC_DEFAULT = 0x00000000,	/* Threshold is 32 DWORDS */