Commit d30fea25 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

PCI/ATS: Show PASID Capability register width in bitmasks 

The PASID Capability and Control registers are both 16 bits wide.  Use
16-bit wide constants in field names to match the register width.  No
functional change intended.

Link: https://lore.kernel.org/r/20231010204436.1000644-5-helgaas@kernel.org


Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarKuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
parent 04e82fa5

include/uapi/linux/pci_regs.h

+5 −5
Original line number Diff line number Diff line
@@ -930,12 +930,12 @@ 


/* Process Address Space ID */

#define PCI_PASID_CAP		0x04    /* PASID feature register */

#define  PCI_PASID_CAP_EXEC	0x02	/* Exec permissions Supported */

#define  PCI_PASID_CAP_PRIV	0x04	/* Privilege Mode Supported */

#define  PCI_PASID_CAP_EXEC	0x0002	/* Exec permissions Supported */

#define  PCI_PASID_CAP_PRIV	0x0004	/* Privilege Mode Supported */

#define PCI_PASID_CTRL		0x06    /* PASID control register */

#define  PCI_PASID_CTRL_ENABLE	0x01	/* Enable bit */

#define  PCI_PASID_CTRL_EXEC	0x02	/* Exec permissions Enable */

#define  PCI_PASID_CTRL_PRIV	0x04	/* Privilege Mode Enable */

#define  PCI_PASID_CTRL_ENABLE	0x0001	/* Enable bit */

#define  PCI_PASID_CTRL_EXEC	0x0002	/* Exec permissions Enable */

#define  PCI_PASID_CTRL_PRIV	0x0004	/* Privilege Mode Enable */

#define PCI_EXT_CAP_PASID_SIZEOF	8



/* Single Root I/O Virtualization */