Unverified Commit d38cc57c authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Krzysztof Wilczyński
Browse files

dt-bindings: PCI: qcom,pcie-sm8550: Add SAR2130P compatible 

On the Qualcomm SAR2130P platform the PCIe host is compatible with the
DWC controller present on the SM8550 platorm, just using one additional
clock.

Link: https://lore.kernel.org/r/20241017-sar2130p-pci-v1-1-5b95e63d9624@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 5efa2322

Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml

+3 −1
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ properties: 
      - const: qcom,pcie-sm8550

      - items:

          - enum:

              - qcom,sar2130p-pcie

              - qcom,pcie-sm8650

          - const: qcom,pcie-sm8550
@@ -39,7 +40,7 @@ properties: 


  clocks:

    minItems: 7

    maxItems: 8

    maxItems: 9



  clock-names:

    minItems: 7
@@ -52,6 +53,7 @@ properties: 
      - const: ddrss_sf_tbu # PCIe SF TBU clock

      - const: noc_aggr # Aggre NoC PCIe AXI clock

      - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock

      - const: qmip_pcie_ahb # QMIP PCIe AHB clock



  interrupts:

    minItems: 8