Commit d39ef5d5 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Move intel_ddi_fdi_post_disable() to fdi code 



Reanme intel_ddi_fdi_post_disable() to hsw_fdi_disable() and
relocate it next to all the other code dealing with FDI_RX.
intel_ddi.c has now been cleansed of FDI_RX.

In order to avoid exposing intel_disable_ddi_buf() outside
intel_ddi.c we can just open code the DDI_BUF_CTL write. The
enable side already has all that stuff open coded so
this actually is more symmetric. But we do need to remeber
to bring the intel_wait_ddi_buf_idle() call over from
inside intel_disable_ddi_buf().

Cc: Dave Airlie <airlied@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211015071625.593-9-ville.syrjala@linux.intel.com


Reviewed-by: default avatarDave Airlie <airlied@redhat.com>
parent 976c68f4

drivers/gpu/drm/i915/display/intel_crt.c

+1 −1
Original line number Diff line number Diff line
@@ -264,7 +264,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state, 
	lpt_disable_pch_transcoder(dev_priv);

	lpt_disable_iclkip(dev_priv);



	intel_ddi_fdi_post_disable(state, encoder, old_crtc_state, old_conn_state);

	hsw_fdi_disable(encoder);



	drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

+1 −36
Original line number Diff line number Diff line
@@ -1939,7 +1939,7 @@ void intel_ddi_enable_clock(struct intel_encoder *encoder, 
		encoder->enable_clock(encoder, crtc_state);

}



static void intel_ddi_disable_clock(struct intel_encoder *encoder)

void intel_ddi_disable_clock(struct intel_encoder *encoder)

{

	if (encoder->disable_clock)

		encoder->disable_clock(encoder);
@@ -2867,41 +2867,6 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state, 
		intel_tc_port_put_link(dig_port);

}



void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,

				struct intel_encoder *encoder,

				const struct intel_crtc_state *old_crtc_state,

				const struct drm_connector_state *old_conn_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u32 val;



	/*

	 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)

	 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,

	 * step 13 is the correct place for it. Step 18 is where it was

	 * originally before the BUN.

	 */

	val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));

	val &= ~FDI_RX_ENABLE;

	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);



	intel_disable_ddi_buf(encoder, old_crtc_state);

	intel_ddi_disable_clock(encoder);



	val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));

	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);

	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);

	intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);



	val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));

	val &= ~FDI_PCDCLK;

	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);



	val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));

	val &= ~FDI_RX_PLL_ENABLE;

	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);

}



static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,

					    struct intel_encoder *encoder,

					    const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_ddi.h

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 
				const struct drm_connector_state *old_conn_state);

void intel_ddi_enable_clock(struct intel_encoder *encoder,

			    const struct intel_crtc_state *crtc_state);

void intel_ddi_disable_clock(struct intel_encoder *encoder);

void intel_ddi_get_clock(struct intel_encoder *encoder,

			 struct intel_crtc_state *crtc_state,

			 struct intel_shared_dpll *pll);

drivers/gpu/drm/i915/display/intel_fdi.c

+37 −0
Original line number Diff line number Diff line
@@ -886,6 +886,43 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, 
		       DP_TP_CTL_ENABLE);

}



void hsw_fdi_disable(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u32 val;



	/*

	 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)

	 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,

	 * step 13 is the correct place for it. Step 18 is where it was

	 * originally before the BUN.

	 */

	val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));

	val &= ~FDI_RX_ENABLE;

	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);



	val = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));

	val &= ~DDI_BUF_CTL_ENABLE;

	intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), val);



	intel_wait_ddi_buf_idle(dev_priv, PORT_E);



	intel_ddi_disable_clock(encoder);



	val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));

	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);

	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);

	intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);



	val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));

	val &= ~FDI_PCDCLK;

	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);



	val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));

	val &= ~FDI_RX_PLL_ENABLE;

	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);

}



void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_fdi.h

+1 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state); 
void intel_fdi_init_hook(struct drm_i915_private *dev_priv);

void hsw_fdi_link_train(struct intel_encoder *encoder,

			const struct intel_crtc_state *crtc_state);

void hsw_fdi_disable(struct intel_encoder *encoder);

void intel_fdi_pll_freq_update(struct drm_i915_private *i915);



void intel_fdi_link_train(struct intel_crtc *crtc,