Commit d3c3c283 authored by Théo Lebrun's avatar Théo Lebrun Committed by Thomas Bogendoerfer
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MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks 



Change the structure of the clock tree: rather than individual
devicetree nodes registering each fixed factor clock derived from OLB
PLLs, have the OLB node provide the necessary clocks.

Remove eyeq5-clocks.dtsi and move the three remaining "fixed-clock"s to
the main eyeq5.dtsi file.

Signed-off-by: default avatarThéo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 56131e6d

arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi

deleted100644 → 0
+0 −270
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

/*

 * Copyright 2023 Mobileye Vision Technologies Ltd.

 */



#include <dt-bindings/clock/mobileye,eyeq5-clk.h>



/ {

	/* Fixed clock */

	xtal: xtal {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <30000000>;

	};



/* PLL_CPU derivatives */

	occ_cpu: occ-cpu {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_CPU>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */

		compatible = "fixed-factor-clock";

		clocks = <&occ_cpu>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	cpc_clk: cpc-clk {

		compatible = "fixed-factor-clock";

		clocks = <&si_css0_ref_clk>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	core0_clk: core0-clk {

		compatible = "fixed-factor-clock";

		clocks = <&si_css0_ref_clk>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	core1_clk: core1-clk {

		compatible = "fixed-factor-clock";

		clocks = <&si_css0_ref_clk>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	core2_clk: core2-clk {

		compatible = "fixed-factor-clock";

		clocks = <&si_css0_ref_clk>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	core3_clk: core3-clk {

		compatible = "fixed-factor-clock";

		clocks = <&si_css0_ref_clk>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	cm_clk: cm-clk {

		compatible = "fixed-factor-clock";

		clocks = <&si_css0_ref_clk>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	mem_clk: mem-clk {

		compatible = "fixed-factor-clock";

		clocks = <&si_css0_ref_clk>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	occ_isram: occ-isram {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_CPU>;

		#clock-cells = <0>;

		clock-div = <2>;

		clock-mult = <1>;

	};

	isram_clk: isram-clk { /* gate ClkRstGen_isram */

		compatible = "fixed-factor-clock";

		clocks = <&occ_isram>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	occ_dbu: occ-dbu {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_CPU>;

		#clock-cells = <0>;

		clock-div = <10>;

		clock-mult = <1>;

	};

	si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */

		compatible = "fixed-factor-clock";

		clocks = <&occ_dbu>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

/* PLL_VDI derivatives */

	occ_vdi: occ-vdi {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_VDI>;

		#clock-cells = <0>;

		clock-div = <2>;

		clock-mult = <1>;

	};

	vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */

		compatible = "fixed-factor-clock";

		clocks = <&occ_vdi>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	occ_can_ser: occ-can-ser {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_VDI>;

		#clock-cells = <0>;

		clock-div = <16>;

		clock-mult = <1>;

	};

	can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */

		compatible = "fixed-factor-clock";

		clocks = <&occ_can_ser>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	i2c_ser_clk: i2c-ser-clk {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_VDI>;

		#clock-cells = <0>;

		clock-div = <20>;

		clock-mult = <1>;

	};

/* PLL_PER derivatives */

	occ_periph: occ-periph {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_PER>;

		#clock-cells = <0>;

		clock-div = <16>;

		clock-mult = <1>;

	};

	periph_clk: periph-clk {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	can_clk: can-clk {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	spi_clk: spi-clk {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	uart_clk: uart-clk {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

	};

	i2c_clk: i2c-clk {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

		clock-output-names = "i2c_clk";

	};

	timer_clk: timer-clk {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

		clock-output-names = "timer_clk";

	};

	gpio_clk: gpio-clk {

		compatible = "fixed-factor-clock";

		clocks = <&occ_periph>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

		clock-output-names = "gpio_clk";

	};

	emmc_sys_clk: emmc-sys-clk {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_PER>;

		#clock-cells = <0>;

		clock-div = <10>;

		clock-mult = <1>;

		clock-output-names = "emmc_sys_clk";

	};

	ccf_ctrl_clk: ccf-ctrl-clk {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_PER>;

		#clock-cells = <0>;

		clock-div = <4>;

		clock-mult = <1>;

		clock-output-names = "ccf_ctrl_clk";

	};

	occ_mjpeg_core: occ-mjpeg-core {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_PER>;

		#clock-cells = <0>;

		clock-div = <2>;

		clock-mult = <1>;

		clock-output-names = "occ_mjpeg_core";

	};

	hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */

		compatible = "fixed-factor-clock";

		clocks = <&occ_mjpeg_core>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

		clock-output-names = "hsm_clk";

	};

	mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */

		compatible = "fixed-factor-clock";

		clocks = <&occ_mjpeg_core>;

		#clock-cells = <0>;

		clock-div = <1>;

		clock-mult = <1>;

		clock-output-names = "mjpeg_core_clk";

	};

	fcmu_a_clk: fcmu-a-clk {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_PER>;

		#clock-cells = <0>;

		clock-div = <20>;

		clock-mult = <1>;

		clock-output-names = "fcmu_a_clk";

	};

	occ_pci_sys: occ-pci-sys {

		compatible = "fixed-factor-clock";

		clocks = <&olb EQ5C_PLL_PER>;

		#clock-cells = <0>;

		clock-div = <8>;

		clock-mult = <1>;

		clock-output-names = "occ_pci_sys";

	};

	pclk: pclk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <250000000>;  /* 250MHz */

	};

	tsu_clk: tsu-clk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <125000000>;  /* 125MHz */

	};

};

arch/mips/boot/dts/mobileye/eyeq5.dtsi

+24 −6
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 


#include <dt-bindings/interrupt-controller/mips-gic.h>



#include "eyeq5-clocks.dtsi"

#include <dt-bindings/clock/mobileye,eyeq5-clk.h>



/ {

	#address-cells = <2>;
@@ -17,7 +17,7 @@ cpu@0 { 
			device_type = "cpu";

			compatible = "img,i6500";

			reg = <0>;

			clocks = <&core0_clk>;

			clocks = <&olb EQ5C_CPU_CORE0>;

		};

	};
@@ -64,6 +64,24 @@ cpu_intc: interrupt-controller { 
		#interrupt-cells = <1>;

	};



	xtal: xtal {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <30000000>;

	};



	pclk: pclk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <250000000>;  /* 250MHz */

	};



	tsu_clk: tsu-clk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <125000000>;  /* 125MHz */

	};



	soc: soc {

		#address-cells = <2>;

		#size-cells = <2>;
@@ -76,7 +94,7 @@ uart0: serial@800000 { 
			reg-io-width = <4>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;

			clocks  = <&uart_clk>, <&occ_periph>;

			clocks  = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;

			clock-names = "uartclk", "apb_pclk";

			resets = <&olb 0 10>;

			pinctrl-names = "default";
@@ -89,7 +107,7 @@ uart1: serial@900000 { 
			reg-io-width = <4>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;

			clocks  = <&uart_clk>, <&occ_periph>;

			clocks  = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;

			clock-names = "uartclk", "apb_pclk";

			resets = <&olb 0 11>;

			pinctrl-names = "default";
@@ -102,7 +120,7 @@ uart2: serial@a00000 { 
			reg-io-width = <4>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;

			clocks  = <&uart_clk>, <&occ_periph>;

			clocks  = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;

			clock-names = "uartclk", "apb_pclk";

			resets = <&olb 0 12>;

			pinctrl-names = "default";
@@ -135,7 +153,7 @@ gic: interrupt-controller@140000 { 
			timer {

				compatible = "mti,gic-timer";

				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;

				clocks = <&core0_clk>;

				clocks = <&olb EQ5C_CPU_CORE0>;

			};

		};

	};