Commit d40371a1 authored by Shengjiu Wang's avatar Shengjiu Wang Committed by Abel Vesa
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clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpll 



According to Reference Manual of i.MX8MP
The parent clock of "earc_phy" is "sai_pll_out_div2",
The parent clock of "audpll" is "osc_24m".

Add CLK_GATE_PARENT() macro for usage of specifying parent clock.

Fixes: 6cd95f7b ("clk: imx: imx8mp: Add audiomix block control")
Signed-off-by: default avatarShengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/1718350923-21392-6-git-send-email-shengjiu.wang@nxp.com


Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
parent dc4211c6

drivers/clk/imx/clk-imx8mp-audiomix.c

+11 −2
Original line number Diff line number Diff line
@@ -156,6 +156,15 @@ static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[] = { 
		PDM_SEL, 2, 0						\

	}



#define CLK_GATE_PARENT(gname, cname, pname)						\

	{								\

		gname"_cg",						\

		IMX8MP_CLK_AUDIOMIX_##cname,				\

		{ .fw_name = pname, .name = pname }, NULL, 1,		\

		CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32),	\

		1, IMX8MP_CLK_AUDIOMIX_##cname % 32			\

	}



struct clk_imx8mp_audiomix_sel {

	const char			*name;

	int				clkid;
@@ -173,14 +182,14 @@ static struct clk_imx8mp_audiomix_sel sels[] = { 
	CLK_GATE("earc", EARC_IPG),

	CLK_GATE("ocrama", OCRAMA_IPG),

	CLK_GATE("aud2htx", AUD2HTX_IPG),

	CLK_GATE("earc_phy", EARC_PHY),

	CLK_GATE_PARENT("earc_phy", EARC_PHY, "sai_pll_out_div2"),

	CLK_GATE("sdma2", SDMA2_ROOT),

	CLK_GATE("sdma3", SDMA3_ROOT),

	CLK_GATE("spba2", SPBA2_ROOT),

	CLK_GATE("dsp", DSP_ROOT),

	CLK_GATE("dspdbg", DSPDBG_ROOT),

	CLK_GATE("edma", EDMA_ROOT),

	CLK_GATE("audpll", AUDPLL_ROOT),

	CLK_GATE_PARENT("audpll", AUDPLL_ROOT, "osc_24m"),

	CLK_GATE("mu2", MU2_ROOT),

	CLK_GATE("mu3", MU3_ROOT),

	CLK_PDM,