Commit d43ce982 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Jakub Kicinski
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dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/T2H and RZ/N2H SoCs 



Add device tree binding support for the Gigabit Ethernet MAC (GMAC) IP
on Renesas RZ/T2H and RZ/N2H SoCs. While these SoCs use the same
Synopsys DesignWare MAC version 5.20 as RZ/V2H, they are synthesized
with different hardware configurations.

Add new compatible strings "renesas,r9a09g077-gbeth" for RZ/T2H and
"renesas,r9a09g087-gbeth" for RZ/N2H, with the latter using RZ/T2H as
fallback since they share identical GMAC IP.

Update the schema to handle hardware differences between SoC variants.
RZ/T2H requires only 3 clocks compared to 7 on RZ/V2H, supports 8 RX/TX
queue pairs instead of 4, and needs 2 reset controls with reset-names
property versus a single unnamed reset. RZ/T2H also has the split header
feature enabled which is disabled on RZ/V2H.

Add support for an optional pcs-handle property to connect the GMAC to
the MIIC PCS converter on RZ/T2H. Use conditional schema validation to
enforce the correct clock, reset, and interrupt configurations per SoC
variant.

Extend the base snps,dwmac.yaml schema to accommodate the increased
interrupt count, supporting up to 19 interrupts and extending the
rx-queue and tx-queue interrupt name patterns to cover queues 0-7.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20250908105901.3198975-2-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent fc006f54

Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml

+138 −40
Original line number Diff line number Diff line
@@ -17,25 +17,36 @@ select: 
          - renesas,r9a09g047-gbeth

          - renesas,r9a09g056-gbeth

          - renesas,r9a09g057-gbeth

          - renesas,r9a09g077-gbeth

          - renesas,r9a09g087-gbeth

          - renesas,rzv2h-gbeth

  required:

    - compatible



properties:

  compatible:

    items:

    oneOf:

      - items:

          - enum:

              - renesas,r9a09g047-gbeth # RZ/G3E

              - renesas,r9a09g056-gbeth # RZ/V2N

              - renesas,r9a09g057-gbeth # RZ/V2H(P)

          - const: renesas,rzv2h-gbeth

          - const: snps,dwmac-5.20

      - items:

          - const: renesas,r9a09g077-gbeth # RZ/T2H

          - const: snps,dwmac-5.20

      - items:

          - const: renesas,r9a09g087-gbeth # RZ/N2H

          - const: renesas,r9a09g077-gbeth

          - const: snps,dwmac-5.20



  reg:

    maxItems: 1



  clocks:

    items:

    oneOf:

      - items:

          - description: CSR clock

          - description: AXI system clock

          - description: PTP clock
@@ -43,9 +54,14 @@ properties: 
          - description: RX clock

          - description: TX clock phase-shifted by 180 degrees

          - description: RX clock phase-shifted by 180 degrees

      - items:

          - description: CSR clock

          - description: AXI system clock

          - description: TX clock



  clock-names:

    items:

    oneOf:

      - items:

          - const: stmmaceth

          - const: pclk

          - const: ptp_ref
@@ -53,12 +69,26 @@ properties: 
          - const: rx

          - const: tx-180

          - const: rx-180



  interrupts:

    minItems: 11

      - items:

          - const: stmmaceth

          - const: pclk

          - const: tx



  interrupt-names:

    items:

    oneOf:

      - items:

          - const: macirq

          - const: eth_wake_irq

          - const: eth_lpi

          - const: rx-queue-0

          - const: rx-queue-1

          - const: rx-queue-2

          - const: rx-queue-3

          - const: tx-queue-0

          - const: tx-queue-1

          - const: tx-queue-2

          - const: tx-queue-3

      - items:

          - const: macirq

          - const: eth_wake_irq

          - const: eth_lpi
@@ -66,14 +96,32 @@ properties: 
          - const: rx-queue-1

          - const: rx-queue-2

          - const: rx-queue-3

          - const: rx-queue-4

          - const: rx-queue-5

          - const: rx-queue-6

          - const: rx-queue-7

          - const: tx-queue-0

          - const: tx-queue-1

          - const: tx-queue-2

          - const: tx-queue-3

          - const: tx-queue-4

          - const: tx-queue-5

          - const: tx-queue-6

          - const: tx-queue-7



  resets:

    items:

    oneOf:

      - items:

          - description: AXI power-on system reset

      - items:

          - description: AXI power-on system reset

          - description: AHB reset



  pcs-handle:

    description:

      phandle pointing to a PCS sub-node compatible with

      Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml#

      (Refer RZ/T2H portion in the DT-binding file)



required:

  - compatible
@@ -87,6 +135,56 @@ required: 
allOf:

  - $ref: snps,dwmac.yaml#



  - if:

      properties:

        compatible:

          contains:

            const: renesas,r9a09g077-gbeth

    then:

      properties:

        clocks:

          maxItems: 3



        clock-names:

          maxItems: 3



        interrupts:

          minItems: 19



        interrupt-names:

          minItems: 19



        resets:

          minItems: 2



        reset-names:

          minItems: 2



      required:

        - reset-names

    else:

      properties:

        clocks:

          minItems: 7



        clock-names:

          minItems: 7



        interrupts:

          minItems: 11

          maxItems: 11



        interrupt-names:

          minItems: 11

          maxItems: 11



        resets:

          maxItems: 1



        pcs-handle: false



        reset-names: false



unevaluatedProperties: false



examples:

Documentation/devicetree/bindings/net/snps,dwmac.yaml

+5 −4
Original line number Diff line number Diff line
@@ -75,6 +75,7 @@ properties: 
        - qcom,sc8280xp-ethqos

        - qcom,sm8150-ethqos

        - renesas,r9a06g032-gmac

        - renesas,r9a09g077-gbeth

        - renesas,rzn1-gmac

        - renesas,rzv2h-gbeth

        - rockchip,px30-gmac
@@ -118,11 +119,11 @@ properties: 


  interrupts:

    minItems: 1

    maxItems: 11

    maxItems: 19



  interrupt-names:

    minItems: 1

    maxItems: 11

    maxItems: 19

    items:

      oneOf:

        - description: Combined signal for various interrupt events
@@ -134,9 +135,9 @@ properties: 
        - description: The interrupt that occurs when HW safety error triggered

          const: sfty

        - description: Per channel receive completion interrupt

          pattern: '^rx-queue-[0-3]$'

          pattern: '^rx-queue-[0-7]$'

        - description: Per channel transmit completion interrupt

          pattern: '^tx-queue-[0-3]$'

          pattern: '^tx-queue-[0-7]$'



  clocks:

    minItems: 1