Commit d472b36e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-5.14-2021-06-16' of... 

Merge tag 'amd-drm-next-5.14-2021-06-16' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-next

amd-drm-next-5.14-2021-06-16:

amdgpu:
- Aldebaran fixes
- Expose asic independent throttler status
- BACO fixes for navi1x
- Smartshift fixes
- Misc code cleanups
- RAS fixes for Sienna Cichlid
- Gamma verificaton fixes
- DC LTTPR fixes
- DP AUX timeout handling fixes
- GFX9, 10 powergating fixes

amdkfd:
- TLB flush fixes when using SDMA
- Locking fixes
- SVM fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210617031719.4013-1-alexander.deucher@amd.com
parents 43ccc783 a4b0b97a

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+18 −31
Original line number Diff line number Diff line
@@ -47,12 +47,6 @@ static struct { 
	spinlock_t mem_limit_lock;

} kfd_mem_limit;



/* Struct used for amdgpu_amdkfd_bo_validate */

struct amdgpu_vm_parser {

	uint32_t        domain;

	bool            wait;

};



static const char * const domain_bit_to_string[] = {

		"CPU",

		"GTT",
@@ -348,11 +342,9 @@ static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain, 
	return ret;

}



static int amdgpu_amdkfd_validate(void *param, struct amdgpu_bo *bo)

static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)

{

	struct amdgpu_vm_parser *p = param;



	return amdgpu_amdkfd_bo_validate(bo, p->domain, p->wait);

	return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);

}



/* vm_validate_pt_pd_bos - Validate page table and directory BOs
@@ -364,28 +356,23 @@ static int amdgpu_amdkfd_validate(void *param, struct amdgpu_bo *bo) 
 */

static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)

{

	struct amdgpu_bo *pd = vm->root.base.bo;

	struct amdgpu_bo *pd = vm->root.bo;

	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);

	struct amdgpu_vm_parser param;

	int ret;



	param.domain = AMDGPU_GEM_DOMAIN_VRAM;

	param.wait = false;



	ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate,

					&param);

	ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL);

	if (ret) {

		pr_err("failed to validate PT BOs\n");

		return ret;

	}



	ret = amdgpu_amdkfd_validate(&param, pd);

	ret = amdgpu_amdkfd_validate_vm_bo(NULL, pd);

	if (ret) {

		pr_err("failed to validate PD\n");

		return ret;

	}



	vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);

	vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);



	if (vm->use_cpu_for_update) {

		ret = amdgpu_bo_kmap(pd, NULL);
@@ -400,7 +387,7 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm) 


static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)

{

	struct amdgpu_bo *pd = vm->root.base.bo;

	struct amdgpu_bo *pd = vm->root.bo;

	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);

	int ret;
@@ -652,7 +639,7 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, 
		}

	}



	gobj = amdgpu_gem_prime_import(&adev->ddev, mem->dmabuf);

	gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);

	if (IS_ERR(gobj))

		return PTR_ERR(gobj);
@@ -1166,7 +1153,7 @@ static int process_sync_pds_resv(struct amdkfd_process_info *process_info, 


	list_for_each_entry(peer_vm, &process_info->vm_list_head,

			    vm_list_node) {

		struct amdgpu_bo *pd = peer_vm->root.base.bo;

		struct amdgpu_bo *pd = peer_vm->root.bo;



		ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,

				       AMDGPU_SYNC_NE_OWNER,
@@ -1233,7 +1220,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, 
	vm->process_info = *process_info;



	/* Validate page directory and attach eviction fence */

	ret = amdgpu_bo_reserve(vm->root.base.bo, true);

	ret = amdgpu_bo_reserve(vm->root.bo, true);

	if (ret)

		goto reserve_pd_fail;

	ret = vm_validate_pt_pd_bos(vm);
@@ -1241,16 +1228,16 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, 
		pr_err("validate_pt_pd_bos() failed\n");

		goto validate_pd_fail;

	}

	ret = amdgpu_bo_sync_wait(vm->root.base.bo,

	ret = amdgpu_bo_sync_wait(vm->root.bo,

				  AMDGPU_FENCE_OWNER_KFD, false);

	if (ret)

		goto wait_pd_fail;

	ret = dma_resv_reserve_shared(vm->root.base.bo->tbo.base.resv, 1);

	ret = dma_resv_reserve_shared(vm->root.bo->tbo.base.resv, 1);

	if (ret)

		goto reserve_shared_fail;

	amdgpu_bo_fence(vm->root.base.bo,

	amdgpu_bo_fence(vm->root.bo,

			&vm->process_info->eviction_fence->base, true);

	amdgpu_bo_unreserve(vm->root.base.bo);

	amdgpu_bo_unreserve(vm->root.bo);



	/* Update process info */

	mutex_lock(&vm->process_info->lock);
@@ -1264,7 +1251,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, 
reserve_shared_fail:

wait_pd_fail:

validate_pd_fail:

	amdgpu_bo_unreserve(vm->root.base.bo);

	amdgpu_bo_unreserve(vm->root.bo);

reserve_pd_fail:

	vm->process_info = NULL;

	if (info) {
@@ -1319,7 +1306,7 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 
				    struct amdgpu_vm *vm)

{

	struct amdkfd_process_info *process_info = vm->process_info;

	struct amdgpu_bo *pd = vm->root.base.bo;

	struct amdgpu_bo *pd = vm->root.bo;



	if (!process_info)

		return;
@@ -1375,7 +1362,7 @@ void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *drm_priv) 
uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)

{

	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);

	struct amdgpu_bo *pd = avm->root.base.bo;

	struct amdgpu_bo *pd = avm->root.bo;

	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);



	if (adev->asic_type < CHIP_VEGA10)
@@ -2402,7 +2389,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef) 
	/* Attach eviction fence to PD / PT BOs */

	list_for_each_entry(peer_vm, &process_info->vm_list_head,

			    vm_list_node) {

		struct amdgpu_bo *bo = peer_vm->root.base.bo;

		struct amdgpu_bo *bo = peer_vm->root.bo;



		amdgpu_bo_fence(bo, &process_info->eviction_fence->base, true);

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+1 −1
Original line number Diff line number Diff line
@@ -832,7 +832,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) 
	if (r)

		return r;



	p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);

	p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);



	if (amdgpu_vm_debug) {

		/* Invalidate all BOs to test for userspace bugs */

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

+2 −2
Original line number Diff line number Diff line
@@ -1304,11 +1304,11 @@ static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused) 


		seq_printf(m, "pid:%d\tProcess:%s ----------\n",

				vm->task_info.pid, vm->task_info.process_name);

		r = amdgpu_bo_reserve(vm->root.base.bo, true);

		r = amdgpu_bo_reserve(vm->root.bo, true);

		if (r)

			break;

		amdgpu_debugfs_vm_bo_info(vm, m);

		amdgpu_bo_unreserve(vm->root.base.bo);

		amdgpu_bo_unreserve(vm->root.bo);

	}



	mutex_unlock(&dev->filelist_mutex);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+3 −2
Original line number Diff line number Diff line
@@ -4124,6 +4124,7 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev) 
{

	struct dma_fence *fence = NULL, *next = NULL;

	struct amdgpu_bo *shadow;

	struct amdgpu_bo_vm *vmbo;

	long r = 1, tmo;



	if (amdgpu_sriov_runtime(adev))
@@ -4133,8 +4134,8 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev) 


	dev_info(adev->dev, "recover vram bo from shadow start\n");

	mutex_lock(&adev->shadow_list_lock);

	list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {



	list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {

		shadow = &vmbo->bo;

		/* No need to recover an evicted BO */

		if (shadow->tbo.resource->mem_type != TTM_PL_TT ||

		    shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+2 −2
Original line number Diff line number Diff line
@@ -325,7 +325,7 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 
	return 0;

}



int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,

int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,

				    int *major, int *minor, int *revision)

{

	struct binary_header *bhdr;
@@ -357,7 +357,7 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, 
		for (j = 0; j < num_ips; j++) {

			ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);



			if (le16_to_cpu(ip->hw_id) == hw_id) {

			if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) {

				if (major)

					*major = ip->major;

				if (minor)