Commit d4b6e7f5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2023-12-21' of... 

Merge tag 'drm-intel-fixes-2023-12-21' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

drm/i915 fixes for v6.7-rc7:
- Fix state readout and check for DSC and bigjoiner combo
- Fix a potential integer overflow
- Reject async flips with bigjoiner
- Fix MTL HDMI/DP PLL clock selection
- Fix various issues by disabling pipe DMC events

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87plyzsnxi.fsf@intel.com
parents b7ef7caf 49e0a85e

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+2 −1
Original line number Diff line number Diff line
@@ -2465,7 +2465,8 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder, 


	val |= XELPDP_FORWARD_CLOCK_UNGATE;



	if (is_hdmi_frl(crtc_state->port_clock))

	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&

	    is_hdmi_frl(crtc_state->port_clock))

		val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK);

	else

		val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);

drivers/gpu/drm/i915/display/intel_display.c

+12 −1
Original line number Diff line number Diff line
@@ -3747,8 +3747,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, 
	if (!active)

		goto out;



	intel_dsc_get_config(pipe_config);

	intel_bigjoiner_get_config(pipe_config);

	intel_dsc_get_config(pipe_config);



	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||

	    DISPLAY_VER(dev_priv) >= 11)
@@ -6033,6 +6033,17 @@ static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 
		return -EINVAL;

	}



	/*

	 * FIXME: Bigjoiner+async flip is busted currently.

	 * Remove this check once the issues are fixed.

	 */

	if (new_crtc_state->bigjoiner_pipes) {

		drm_dbg_kms(&i915->drm,

			    "[CRTC:%d:%s] async flip disallowed with bigjoiner\n",

			    crtc->base.base.id, crtc->base.name);

		return -EINVAL;

	}



	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,

					     new_plane_state, i) {

		if (plane->pipe != crtc->pipe)

drivers/gpu/drm/i915/display/intel_dmc.c

+41 −2
Original line number Diff line number Diff line
@@ -389,7 +389,7 @@ disable_all_flip_queue_events(struct drm_i915_private *i915) 
	enum intel_dmc_id dmc_id;



	/* TODO: check if the following applies to all D13+ platforms. */

	if (!IS_DG2(i915) && !IS_TIGERLAKE(i915))

	if (!IS_TIGERLAKE(i915))

		return;



	for_each_dmc_id(dmc_id) {
@@ -493,6 +493,45 @@ void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe) 
		intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);

}



static bool is_dmc_evt_ctl_reg(struct drm_i915_private *i915,

			       enum intel_dmc_id dmc_id, i915_reg_t reg)

{

	u32 offset = i915_mmio_reg_offset(reg);

	u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, 0));

	u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));



	return offset >= start && offset < end;

}



static bool disable_dmc_evt(struct drm_i915_private *i915,

			    enum intel_dmc_id dmc_id,

			    i915_reg_t reg, u32 data)

{

	if (!is_dmc_evt_ctl_reg(i915, dmc_id, reg))

		return false;



	/* keep all pipe DMC events disabled by default */

	if (dmc_id != DMC_FW_MAIN)

		return true;



	return false;

}



static u32 dmc_mmiodata(struct drm_i915_private *i915,

			struct intel_dmc *dmc,

			enum intel_dmc_id dmc_id, int i)

{

	if (disable_dmc_evt(i915, dmc_id,

			    dmc->dmc_info[dmc_id].mmioaddr[i],

			    dmc->dmc_info[dmc_id].mmiodata[i]))

		return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,

				      DMC_EVT_CTL_TYPE_EDGE_0_1) |

			REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,

				       DMC_EVT_CTL_EVENT_ID_FALSE);

	else

		return dmc->dmc_info[dmc_id].mmiodata[i];

}



/**

 * intel_dmc_load_program() - write the firmware from memory to register.

 * @i915: i915 drm device.
@@ -532,7 +571,7 @@ void intel_dmc_load_program(struct drm_i915_private *i915) 
	for_each_dmc_id(dmc_id) {

		for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {

			intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i],

				       dmc->dmc_info[dmc_id].mmiodata[i]);

				       dmc_mmiodata(i915, dmc, dmc_id, i));

		}

	}

drivers/gpu/drm/i915/i915_hwmon.c

+2 −2
Original line number Diff line number Diff line
@@ -175,7 +175,7 @@ hwm_power1_max_interval_show(struct device *dev, struct device_attribute *attr, 
	 *     tau4 = (4 | x) << y

	 * but add 2 when doing the final right shift to account for units

	 */

	tau4 = ((1 << x_w) | x) << y;

	tau4 = (u64)((1 << x_w) | x) << y;

	/* val in hwmon interface units (millisec) */

	out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
@@ -211,7 +211,7 @@ hwm_power1_max_interval_store(struct device *dev, 
	r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);

	x = REG_FIELD_GET(PKG_MAX_WIN_X, r);

	y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);

	tau4 = ((1 << x_w) | x) << y;

	tau4 = (u64)((1 << x_w) | x) << y;

	max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);



	if (val > max_win)