Commit d4c515a2 authored by Brian Masney's avatar Brian Masney
Browse files

clk: sophgo: sg2042-pll: remove round_rate() in favor of determine_rate() 



This driver implements both the determine_rate() and round_rate() clk
ops, and the round_rate() clk ops is deprecated. When both are defined,
clk_core_determine_round_nolock() from the clk core will only use the
determine_rate() clk ops, so let's remove the round_rate() clk ops since
it's unused.

The implementation of sg2042_clk_pll_determine_rate() calls
sg2042_clk_pll_round_rate(), so this folds the two into a single
function.

Reviewed-by: default avatarChen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox
Signed-off-by: default avatarBrian Masney <bmasney@redhat.com>
parent 9a3b6993

drivers/clk/sophgo/clk-sg2042-pll.c

+9 −17
Original line number Diff line number Diff line
@@ -346,37 +346,30 @@ static unsigned long sg2042_clk_pll_recalc_rate(struct clk_hw *hw, 
	return rate;

}



static long sg2042_clk_pll_round_rate(struct clk_hw *hw,

				      unsigned long req_rate,

				      unsigned long *prate)

static int sg2042_clk_pll_determine_rate(struct clk_hw *hw,

					 struct clk_rate_request *req)

{

	struct sg2042_pll_ctrl pctrl_table;

	unsigned int value;

	long proper_rate;

	int ret;



	ret = sg2042_get_pll_ctl_setting(&pctrl_table, req_rate, *prate);

	ret = sg2042_get_pll_ctl_setting(&pctrl_table,

					 min(req->rate, req->max_rate),

					 req->best_parent_rate);

	if (ret) {

		proper_rate = 0;

		goto out;

	}



	value = sg2042_pll_ctrl_encode(&pctrl_table);

	proper_rate = (long)sg2042_pll_recalc_rate(value, *prate);

	proper_rate = (long)sg2042_pll_recalc_rate(value, req->best_parent_rate);



out:

	pr_debug("--> %s: pll_round_rate: val = %ld\n",

	pr_debug("--> %s: pll_determine_rate: val = %ld\n",

		 clk_hw_get_name(hw), proper_rate);

	return proper_rate;

}

	req->rate = proper_rate;



static int sg2042_clk_pll_determine_rate(struct clk_hw *hw,

					 struct clk_rate_request *req)

{

	req->rate = sg2042_clk_pll_round_rate(hw, min(req->rate, req->max_rate),

					      &req->best_parent_rate);

	pr_debug("--> %s: pll_determine_rate: val = %ld\n",

		 clk_hw_get_name(hw), req->rate);

	return 0;

}
@@ -417,14 +410,13 @@ static int sg2042_clk_pll_set_rate(struct clk_hw *hw, 


static const struct clk_ops sg2042_clk_pll_ops = {

	.recalc_rate = sg2042_clk_pll_recalc_rate,

	.round_rate = sg2042_clk_pll_round_rate,

	.determine_rate = sg2042_clk_pll_determine_rate,

	.set_rate = sg2042_clk_pll_set_rate,

};



static const struct clk_ops sg2042_clk_pll_ro_ops = {

	.recalc_rate = sg2042_clk_pll_recalc_rate,

	.round_rate = sg2042_clk_pll_round_rate,

	.determine_rate = sg2042_clk_pll_determine_rate,

};



/*