Commit d51309b4 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: move and group cdclk under display.cdclk 



Move display cdclk related members under drm_i915_private display
sub-struct.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/7df23655be5dc70fb1a2b43ce41e1682e40395d8.1661779055.git.jani.nikula@intel.com
parent 7249dfcb

drivers/gpu/drm/i915/display/hsw_ips.c

+1 −1
Original line number Diff line number Diff line
@@ -202,7 +202,7 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) 
	 * Should measure whether using a lower cdclk w/o IPS

	 */

	if (IS_BROADWELL(i915) &&

	    crtc_state->pixel_rate > i915->max_cdclk_freq * 95 / 100)

	    crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100)

		return false;



	return true;

drivers/gpu/drm/i915/display/intel_audio.c

+3 −3
Original line number Diff line number Diff line
@@ -532,7 +532,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, 
	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;

	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;

	vdsc_bpp = crtc_state->dsc.compressed_bpp;

	cdclk = i915->cdclk.hw.cdclk;

	cdclk = i915->display.cdclk.hw.cdclk;

	/* fec= 0.972261, using rounding multiplier of 1000000 */

	fec_coeff = 972261;

	link_clk = crtc_state->port_clock;
@@ -971,7 +971,7 @@ void intel_audio_cdclk_change_post(struct drm_i915_private *i915) 
	struct aud_ts_cdclk_m_n aud_ts;



	if (DISPLAY_VER(i915) >= 13) {

		get_aud_ts_cdclk_m_n(i915->cdclk.hw.ref, i915->cdclk.hw.cdclk, &aud_ts);

		get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts);



		intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n);

		intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN);
@@ -1119,7 +1119,7 @@ static int i915_audio_component_get_cdclk_freq(struct device *kdev) 
	if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv)))

		return -ENODEV;



	return dev_priv->cdclk.hw.cdclk;

	return dev_priv->display.cdclk.hw.cdclk;

}



/*

drivers/gpu/drm/i915/display/intel_backlight.c

+2 −2
Original line number Diff line number Diff line
@@ -1113,7 +1113,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) 
	if (IS_PINEVIEW(dev_priv))

		clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);

	else

		clock = KHz(dev_priv->cdclk.hw.cdclk);

		clock = KHz(dev_priv->display.cdclk.hw.cdclk);



	return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 32);

}
@@ -1131,7 +1131,7 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) 
	if (IS_G4X(dev_priv))

		clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);

	else

		clock = KHz(dev_priv->cdclk.hw.cdclk);

		clock = KHz(dev_priv->display.cdclk.hw.cdclk);



	return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 128);

}

drivers/gpu/drm/i915/display/intel_cdclk.c

+103 −103

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/i915/display/intel_cdclk.h

+2 −2
Original line number Diff line number Diff line
@@ -77,9 +77,9 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state); 


#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)

#define intel_atomic_get_old_cdclk_state(state) \

	to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))

	to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))

#define intel_atomic_get_new_cdclk_state(state) \

	to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))

	to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))



int intel_cdclk_init(struct drm_i915_private *dev_priv);