Commit d51f8f63 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mailbox-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox 

Pull mailbox updates from Jassi Brar:
 "broadcom:
   - remove unused pdc_dma_map

  imx:
   - fix TXDB_V2 channel race condition

  mediatek:
   - cleanup and refactor driver
   - add bindings for gce-props

  omap:
   - fix mailbox interrupt sharing

  qcom:
   - add bindings for SA8775p
   - add CPUCP driver

  zynqmp:
   - make polling period configurable"

* tag 'mailbox-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox:
  mailbox: mtk-cmdq: Move devm_mbox_controller_register() after devm_pm_runtime_enable()
  mailbox: zynqmp-ipi: Make polling period configurable
  mailbox: qcom-cpucp: fix 64BIT dependency
  mailbox: Add support for QTI CPUCP mailbox controller
  dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings
  dt-bindings: remoteproc: qcom,sa8775p-pas: Document the SA8775p ADSP, CDSP and GPDSP
  mailbox: mtk-cmdq: add missing MODULE_DESCRIPTION() macro
  mailbox: bcm-pdc: remove unused struct 'pdc_dma_map'
  mailbox: imx: fix TXDB_V2 channel race condition
  mailbox: omap: Fix mailbox interrupt sharing
  mailbox: mtk-cmdq: Dynamically allocate clk_bulk_data structure
  mailbox: mtk-cmdq: Move and partially refactor clocks probe
  mailbox: mtk-cmdq: Stop requiring name for GCE clock
  dt-bindings: mailbox: Add mediatek,gce-props.yaml
parents 71bed1ec a8bd68e4

Documentation/devicetree/bindings/mailbox/mediatek,gce-props.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mailbox/mediatek,gce-props.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek Global Command Engine Common Properties



maintainers:

  - Houlong Wei <houlong.wei@mediatek.com>



description:

  The Global Command Engine (GCE) is an instruction based, multi-threaded,

  single-core command dispatcher for MediaTek hardware. The Command Queue

  (CMDQ) mailbox driver is a driver for GCE, implemented using the Linux

  mailbox framework. It is used to receive messages from mailbox consumers

  and configure GCE to execute the specified instruction set in the message.

  We use mediatek,gce-mailbox.yaml to define the properties for CMDQ mailbox

  driver. A device driver that uses the CMDQ driver to configure its hardware

  registers is a mailbox consumer. The mailbox consumer can request a mailbox

  channel corresponding to a GCE hardware thread to send a message, specifying

  that the GCE thread to configure its hardware. The mailbox provider can also

  reserve a mailbox channel to configure GCE hardware register by the specific

  GCE thread. This binding defines the common GCE properties for both mailbox

  provider and consumers.



properties:

  mediatek,gce-events:

    description:

      GCE has an event table in SRAM, consisting of 1024 event IDs (0~1023).

      Each event ID has a boolean event value with the default value 0.

      The property mediatek,gce-events is used to obtain the event IDs.

      Some gce-events are hardware-bound and cannot be changed by software.

      For instance, in MT8195, when VDO0_MUTEX is stream done, VDO_MUTEX will

      send an event signal to GCE, setting the value of event ID 597 to 1.

      Similarly, in MT8188, the value of event ID 574 will be set to 1 when

      VOD0_MUTEX is stream done.

      On the other hand, some gce-events are not hardware-bound and can be

      changed by software. For example, in MT8188, we can set the value of

      event ID 855, which is not bound to any hardware, to 1 when the driver

      in the secure world completes a task. However, in MT8195, event ID 855

      is already bound to VDEC_LAT1, so we need to select another event ID to

      achieve the same purpose. This event ID can be any ID that is not bound

      to any hardware and is not yet used in any software driver.

      To determine if the event ID is bound to the hardware or used by a

      software driver, refer to the GCE header

      include/dt-bindings/gce/<chip>-gce.h of each chip.

    $ref: /schemas/types.yaml#/definitions/uint32-array

    minItems: 1

    maxItems: 32



additionalProperties: true

Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller



maintainers:

  - Sibi Sankar <quic_sibis@quicinc.com>



description:

  The CPUSS Control Processor (CPUCP) mailbox controller enables communication

  between AP and CPUCP by acting as a doorbell between them.



properties:

  compatible:

    items:

      - const: qcom,x1e80100-cpucp-mbox



  reg:

    items:

      - description: CPUCP rx register region

      - description: CPUCP tx register region



  interrupts:

    maxItems: 1



  "#mbox-cells":

    const: 1



required:

  - compatible

  - reg

  - interrupts

  - "#mbox-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    mailbox@17430000 {

        compatible = "qcom,x1e80100-cpucp-mbox";

        reg = <0x17430000 0x10000>, <0x18830000 0x10000>;

        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;

        #mbox-cells = <1>;

    };

Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/remoteproc/qcom,sa8775p-pas.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SA8775p Peripheral Authentication Service



maintainers:

  - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>



description:

  Qualcomm SA8775p SoC Peripheral Authentication Service loads and boots firmware

  on the Qualcomm DSP Hexagon cores.



properties:

  compatible:

    enum:

      - qcom,sa8775p-adsp-pas

      - qcom,sa8775p-cdsp0-pas

      - qcom,sa8775p-cdsp1-pas

      - qcom,sa8775p-gpdsp0-pas

      - qcom,sa8775p-gpdsp1-pas



  reg:

    maxItems: 1



  clocks:

    items:

      - description: XO clock



  clock-names:

    items:

      - const: xo



  qcom,qmp:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: Reference to the AOSS side-channel message RAM.



  firmware-name:

    $ref: /schemas/types.yaml#/definitions/string-array

    items:

      - description: Firmware name of the Hexagon core



  memory-region:

    items:

      - description: Memory region for main Firmware authentication



  interrupts:

    maxItems: 5



  interrupt-names:

    maxItems: 5



required:

  - compatible

  - reg

  - memory-region



allOf:

  - $ref: /schemas/remoteproc/qcom,pas-common.yaml#



  - if:

      properties:

        compatible:

          enum:

            - qcom,sa8775p-adsp-pas

    then:

      properties:

        power-domains:

          items:

            - description: LCX power domain

            - description: LMX power domain

        power-domain-names:

          items:

            - const: lcx

            - const: lmx



  - if:

      properties:

        compatible:

          enum:

            - qcom,sa8775p-cdsp0-pas

            - qcom,sa8775p-cdsp1-pas

    then:

      properties:

        power-domains:

          items:

            - description: CX power domain

            - description: MXC power domain

            - description: NSP0 power domain

        power-domain-names:

          items:

            - const: cx

            - const: mxc

            - const: nsp



  - if:

      properties:

        compatible:

          enum:

            - qcom,sa8775p-gpdsp0-pas

            - qcom,sa8775p-gpdsp1-pas

    then:

      properties:

        power-domains:

          items:

            - description: CX power domain

            - description: MXC power domain

        power-domain-names:

          items:

            - const: cx

            - const: mxc



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/mailbox/qcom-ipcc.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>



    remoteproc@30000000 {

        compatible = "qcom,sa8775p-adsp-pas";

        reg = <0x30000000 0x100>;



        interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,

                              <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,

                              <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,

                              <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,

                              <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;

        interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";



        clocks = <&rpmhcc RPMH_CXO_CLK>;

        clock-names = "xo";



        power-domains = <&rpmhpd RPMHPD_LCX>, <&rpmhpd RPMHPD_LMX>;

        power-domain-names = "lcx", "lmx";



        interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;



        memory-region = <&pil_adsp_mem>;



        qcom,qmp = <&aoss_qmp>;



        qcom,smem-states = <&smp2p_adsp_out 0>;

        qcom,smem-state-names = "stop";



        glink-edge {

            interrupts-extended = <&ipcc IPCC_CLIENT_LPASS

                                   IPCC_MPROC_SIGNAL_GLINK_QMP

                                   IRQ_TYPE_EDGE_RISING>;

            mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>;



            label = "lpass";

            qcom,remote-pid = <2>;

        };

    };

MAINTAINERS

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@@ -18749,6 +18749,13 @@ S: Maintained 
F:	Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml

F:	drivers/pmdomain/qcom/cpr.c









QUALCOMM CPUCP MAILBOX DRIVER









M:	Sibi Sankar <quic_sibis@quicinc.com>









L:	linux-arm-msm@vger.kernel.org









S:	Supported









F:	Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml









F:	drivers/mailbox/qcom-cpucp-mbox.c

















QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096









M:	Ilia Lin <ilia.lin@kernel.org>









L:	linux-pm@vger.kernel.org

























drivers/mailbox/Kconfig



+8
−0






























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@@ -276,6 +276,14 @@ config SPRD_MBOX







	  to send message between application processors and MCU. Say Y here if









	  you want to build the Spreatrum mailbox controller driver.



















config QCOM_CPUCP_MBOX









	tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"









	depends on (ARCH_QCOM || COMPILE_TEST) && 64BIT









	help









	  Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox









	  controller driver enables communication between AP and CPUCP. Say









	  Y here if you want to build this driver.



















config QCOM_IPCC









	tristate "Qualcomm Technologies, Inc. IPCC driver"









	depends on ARCH_QCOM || COMPILE_TEST