Commit d7169b8b authored by Val Packett's avatar Val Packett Committed by Heiko Stuebner
Browse files

clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066 



RK3066 has two "CIF" video capture interface blocks, reference the
newly added IDs for their PCLK clocks.

Signed-off-by: default avatarVal Packett <val@packett.cool>
Link: https://lore.kernel.org/r/20241205182954.5346-2-val@packett.cool


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 7c980403

drivers/clk/rockchip/clk-rk3188.c

+2 −2
Original line number Diff line number Diff line
@@ -337,7 +337,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 


	GATE(0, "pclkin_cif0", "ext_cif0", 0,

			RK2928_CLKGATE_CON(3), 3, GFLAGS),

	INVERTER(0, "pclk_cif0", "pclkin_cif0",

	INVERTER(PCLK_CIF0, "pclk_cif0", "pclkin_cif0",

			RK2928_CLKSEL_CON(30), 8, IFLAGS),



	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
@@ -595,7 +595,7 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { 


	GATE(0, "pclkin_cif1", "ext_cif1", 0,

			RK2928_CLKGATE_CON(3), 4, GFLAGS),

	INVERTER(0, "pclk_cif1", "pclkin_cif1",

	INVERTER(PCLK_CIF1, "pclk_cif1", "pclkin_cif1",

			RK2928_CLKSEL_CON(30), 12, IFLAGS),



	COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,