Commit d728fd03 authored by Austin Zheng's avatar Austin Zheng Committed by Alex Deucher
Browse files

drm/amd/display: Setup Second Stutter Watermark Implementation 



[WHY & HOW]
Setup initial changes required to program another set of watermarks
for a 2nd stutter mode. The 2nd stutter mode will be lower power but
have higher enter/exit latencies.

PMFW to choose which stutter mode to use based on stutter efficiences
to see if original stutter (LP1) or low power stutter (LP2) will result
in better power savings.

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarAustin Zheng <Austin.Zheng@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 421507ad

drivers/gpu/drm/amd/display/dc/dc.h

+9 −0
Original line number Diff line number Diff line
@@ -694,6 +694,15 @@ struct dc_clocks { 
	int idle_fclk_khz;

	int subvp_prefetch_dramclk_khz;

	int subvp_prefetch_fclk_khz;



	/* Stutter efficiency is technically not clock values

	 * but stored here so the values are part of the update_clocks call similar to num_ways

	 * Efficiencies are stored as percentage (0-100)

	 */

	struct {

		uint8_t base_efficiency; //LP1

		uint8_t low_power_efficiency; //LP2

	} stutter_efficiency;

};



struct dc_bw_validation_profile {

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

+2 −0
Original line number Diff line number Diff line
@@ -1165,6 +1165,8 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state 
	context->bw_ctx.bw.dcn.clk.socclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.socclk_khz;

	context->bw_ctx.bw.dcn.clk.subvp_prefetch_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz;

	context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz;

	context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency;

	context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency;

}



static struct dml2_dchub_watermark_regs *wm_set_index_to_dc_wm_set(union dcn_watermark_set *watermarks, const enum dml2_dchub_watermark_reg_set_index wm_index)

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

+2 −0
Original line number Diff line number Diff line
@@ -159,6 +159,8 @@ struct dml2_dchub_watermark_regs { 
	uint32_t sr_exit;

	uint32_t sr_enter_z8;

	uint32_t sr_exit_z8;

	uint32_t sr_enter_low_power;

	uint32_t sr_exit_low_power;

	uint32_t uclk_pstate;

	uint32_t fclk_pstate;

	uint32_t temp_read_or_ppt;

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h

+2 −0
Original line number Diff line number Diff line
@@ -96,6 +96,8 @@ struct dml2_soc_power_management_parameters { 
	double g7_temperature_read_blackout_us;

	double stutter_enter_plus_exit_latency_us;

	double stutter_exit_latency_us;

	double low_power_stutter_enter_plus_exit_latency_us;

	double low_power_stutter_exit_latency_us;

	double z8_stutter_enter_plus_exit_latency_us;

	double z8_stutter_exit_latency_us;

	double z8_min_idle_time;

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

+2 −0
Original line number Diff line number Diff line
@@ -417,6 +417,8 @@ struct dml2_display_cfg_programming { 


	struct {

		bool supported_in_blank; // Changing to configurations where this is false requires stutter to be disabled during the transition

		uint8_t base_percent_efficiency; //LP1

		uint8_t low_power_percent_efficiency; //LP2

	} stutter;



	struct {