Merge branches 'fixes' and 'misc' into for-linus

	select HAVE_ARCH_PFN_VALID

	select HAVE_ARCH_SECCOMP

	select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT

	select HAVE_ARCH_STACKLEAK

	select HAVE_ARCH_THREAD_STRUCT_WHITELIST

	select HAVE_ARCH_TRACEHOOK

	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE

	select HAVE_KERNEL_XZ

	select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M

	select HAVE_KRETPROBES if HAVE_KPROBES

	select HAVE_LD_DEAD_CODE_DATA_ELIMINATION

	select HAVE_MOD_ARCH_SPECIFIC

	select HAVE_NMI

	select HAVE_OPTPROBES if !THUMB2_KERNEL

	bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"

	depends on CPU_V7

	help

	  This option enables the workaround for the 764319 Cortex A-9 erratum.

	  This option enables the workaround for the 764319 Cortex-A9 erratum.

	  CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an

	  unexpected Undefined Instruction exception when the DBGSWENABLE

	  external pin is set to 0, even when the CP14 accesses are performed

HEAD	= head.o

OBJS	+= misc.o decompress.o

CFLAGS_decompress.o += $(DISABLE_STACKLEAK_PLUGIN)

ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y)

OBJS	+= debug.o

AFLAGS_head.o += -DDEBUG

  . = BSS_START;

  __bss_start = .;

  .bss			: { *(.bss) }

  .bss			: { *(.bss .bss.*) }

  _end = .;

  . = ALIGN(8);		/* the stack must be 64-bit aligned */

#endif

};

static inline bool on_thread_stack(void)

{

	unsigned long delta = current_stack_pointer ^ (unsigned long)current->stack;

	return delta < THREAD_SIZE;

}

static __always_inline

void arm_get_current_stackframe(struct pt_regs *regs, struct stackframe *frame)

{

#define PROC_INFO							\

		. = ALIGN(4);						\

		__proc_info_begin = .;					\

		*(.proc.info.init)					\

		KEEP(*(.proc.info.init))				\

		__proc_info_end = .;

#define IDMAP_TEXT							\