Commit d7b9056c authored by Alok Tiwari's avatar Alok Tiwari Committed by Dave Jiang
Browse files

cxl/edac: Use correct format specifier for u32 val 



The dev_dbg() message in cxl_set_ecs_threshold() used %d for
an unsigned value, which could lead to incorrect logging.
Update the format specifier to %u to match variable type.

Signed-off-by: default avatarAlok Tiwari <alok.a.tiwari@oracle.com>
Reviewed-by: default avatarShiju Jose <shiju.jose@huawei.com>
Reviewed-by: default avatarAlison Schofield <alison.schofield@intel.com?>
Reviewed-by: default avatarIra Weiny <ira.weiny@intel.com>
Link: https://patch.msgid.link/20250622183919.4156343-1-alok.a.tiwari@oracle.com


Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
parent 8ad85794

drivers/cxl/core/edac.c

+1 −1
Original line number Diff line number Diff line
@@ -697,7 +697,7 @@ static int cxl_set_ecs_threshold(struct device *dev, u8 *log_cap, u16 *config, 
				      ECS_THRESHOLD_IDX_4096);

		break;

	default:

		dev_dbg(dev, "Invalid CXL ECS threshold count(%d) to set\n",

		dev_dbg(dev, "Invalid CXL ECS threshold count(%u) to set\n",

			val);

		dev_dbg(dev, "Supported ECS threshold counts: %u, %u, %u\n",

			ECS_THRESHOLD_256, ECS_THRESHOLD_1024,