Commit d7f12857 authored by Bo Gan's avatar Bo Gan Committed by Stephen Boyd
Browse files

clk: analogbits: Fix incorrect calculation of vco rate delta 



In wrpll_configure_for_rate() we try to determine the best PLL
configuration for a target rate. However, in the loop where we try
values of R, we should compare the derived `vco` with `target_vco_rate`.
However, we were in fact comparing it with `target_rate`, which is
actually after Q shift. This is incorrect, and sometimes can result in
suboptimal clock rates. Fix it.

Fixes: 7b9487a9 ("clk: analogbits: add Wide-Range PLL library")
Signed-off-by: default avatarBo Gan <ganboing@gmail.com>
Link: https://lore.kernel.org/r/20240830061639.2316-1-ganboing@gmail.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent ab9f0d04

drivers/clk/analogbits/wrpll-cln28hpc.c

+1 −1
Original line number Diff line number Diff line
@@ -292,7 +292,7 @@ int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate, 
			vco = vco_pre * f;

		}



		delta = abs(target_rate - vco);

		delta = abs(target_vco_rate - vco);

		if (delta < best_delta) {

			best_delta = delta;

			best_r = r;