Commit d7f6f07e authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/mediatek' 

- Remove leftover mac_reset assert for Airoha EN7581 SoC (Lorenzo Bianconi)

- Add EN7581 PBUS controller 'mediatek,pbus-csr' DT property and program
  host bridge memory aperture to this syscon node (Lorenzo Bianconi)

* pci/controller/mediatek:
  PCI: mediatek-gen3: Fix inconsistent indentation
  PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581 SoC
  dt-bindings: PCI: mediatek-gen3: Add mediatek,pbus-csr phandle array property
  PCI: mediatek-gen3: Remove leftover mac_reset assert for Airoha EN7581 SoC
parents 5edeea2d 98e87cc5

Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

+17 −0
Original line number Diff line number Diff line
@@ -109,6 +109,17 @@ properties: 
  power-domains:

    maxItems: 1



  mediatek,pbus-csr:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: phandle to pbus-csr syscon

          - description: offset of pbus-csr base address register

          - description: offset of pbus-csr base address mask register

    description:

      Phandle with two arguments to the syscon node used to detect if

      a given address is accessible on PCIe controller.



  '#interrupt-cells':

    const: 1
@@ -168,6 +179,8 @@ allOf: 
          minItems: 1

          maxItems: 2



        mediatek,pbus-csr: false



  - if:

      properties:

        compatible:
@@ -197,6 +210,8 @@ allOf: 
          minItems: 1

          maxItems: 2



        mediatek,pbus-csr: false



  - if:

      properties:

        compatible:
@@ -224,6 +239,8 @@ allOf: 
          minItems: 1

          maxItems: 2



        mediatek,pbus-csr: false



  - if:

      properties:

        compatible:

drivers/pci/controller/pcie-mediatek-gen3.c

+49 −15
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/irqchip/chained_irq.h>

#include <linux/irqdomain.h>

#include <linux/kernel.h>

#include <linux/mfd/syscon.h>

#include <linux/module.h>

#include <linux/msi.h>

#include <linux/of_device.h>
@@ -24,6 +25,7 @@ 
#include <linux/platform_device.h>

#include <linux/pm_domain.h>

#include <linux/pm_runtime.h>

#include <linux/regmap.h>

#include <linux/reset.h>



#include "../pci.h"
@@ -352,7 +354,8 @@ static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie, 


		dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n",

			range_type, *num, (unsigned long long)cpu_addr,

			(unsigned long long)pci_addr, (unsigned long long)table_size);

			(unsigned long long)pci_addr,

			(unsigned long long)table_size);



		cpu_addr += table_size;

		pci_addr += table_size;
@@ -887,7 +890,8 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) 
	for (i = 0; i < num_resets; i++)

		pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i];



	ret = devm_reset_control_bulk_get_optional_shared(dev, num_resets, pcie->phy_resets);

	ret = devm_reset_control_bulk_get_optional_shared(dev, num_resets,

							  pcie->phy_resets);

	if (ret) {

		dev_err(dev, "failed to get PHY bulk reset\n");

		return ret;
@@ -919,7 +923,8 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) 


	ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes);

	if (ret == 0) {

	       if (num_lanes == 0 || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2))

		if (num_lanes == 0 || num_lanes > 16 ||

		    (num_lanes != 1 && num_lanes % 2))

			dev_warn(dev, "invalid num-lanes, using controller defaults\n");

		else

			pcie->num_lanes = num_lanes;
@@ -930,9 +935,13 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) 


static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)

{

	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);

	struct device *dev = pcie->dev;

	struct resource_entry *entry;

	struct regmap *pbus_regmap;

	u32 val, args[2], size;

	resource_size_t addr;

	int err;

	u32 val;



	/*

	 * The controller may have been left out of reset by the bootloader
@@ -940,11 +949,30 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) 
	 */

	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,

				  pcie->phy_resets);

	reset_control_assert(pcie->mac_reset);



	/* Wait for the time needed to complete the reset lines assert. */

	msleep(PCIE_EN7581_RESET_TIME_MS);



	/*

	 * Configure PBus base address and base address mask to allow the

	 * hw to detect if a given address is accessible on PCIe controller.

	 */

	pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node,

							   "mediatek,pbus-csr",

							   ARRAY_SIZE(args),

							   args);

	if (IS_ERR(pbus_regmap))

		return PTR_ERR(pbus_regmap);



	entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);

	if (!entry)

		return -ENODEV;



	addr = entry->res->start - entry->offset;

	regmap_write(pbus_regmap, args[0], lower_32_bits(addr));

	size = lower_32_bits(resource_size(entry->res));

	regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size)));



	/*

	 * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581

	 * requires PHY initialization and power-on before PHY reset deassert.
@@ -961,7 +989,8 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) 
		goto err_phy_on;

	}



	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);

	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets,

					  pcie->phy_resets);

	if (err) {

		dev_err(dev, "failed to deassert PHYs\n");

		goto err_phy_deassert;
@@ -1006,7 +1035,8 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) 
err_clk_prepare_enable:

	pm_runtime_put_sync(dev);

	pm_runtime_disable(dev);

	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);

	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,

				  pcie->phy_resets);

err_phy_deassert:

	phy_power_off(pcie->phy);

err_phy_on:
@@ -1030,7 +1060,8 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) 
	usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US);



	/* PHY power on and enable pipe clock */

	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);

	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets,

					  pcie->phy_resets);

	if (err) {

		dev_err(dev, "failed to deassert PHYs\n");

		return err;
@@ -1070,7 +1101,8 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) 
err_phy_on:

	phy_exit(pcie->phy);

err_phy_init:

	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);

	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,

				  pcie->phy_resets);



	return err;

}
@@ -1085,7 +1117,8 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie) 


	phy_power_off(pcie->phy);

	phy_exit(pcie->phy);

	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);

	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,

				  pcie->phy_resets);

}



static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pcie)
@@ -1112,7 +1145,8 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) 
	 * Deassert the line in order to avoid unbalance in deassert_count

	 * counter since the bulk is shared.

	 */

	reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);

	reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets,

				    pcie->phy_resets);



	/* Don't touch the hardware registers before power up */

	err = pcie->soc->power_up(pcie);