Commit d8555714 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v6.10-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 

Pull Amlogic clk driver updates from Jerome Brunet:

 - s4/a1: add regmap maximum register for proper debugfs dump
 - s4: add MODULE_DEVICE_TABLE() on pll and periph controllers
 - pll driver: print clock name on lock error to help debug
 - vclk: finish dsi clock path support
 - license: fix occurence "GPL v2" as reported by checkpatch

* tag 'clk-meson-v6.10-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: s4: fix module autoloading
  clk: meson: fix module license to GPL only
  clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF
  clk: meson: add vclk driver
  clk: meson: pll: print out pll name when unable to lock it
  clk: meson: s4: pll: determine maximum register in regmap config
  clk: meson: s4: peripherals: determine maximum register in regmap config
  clk: meson: a1: pll: determine maximum register in regmap config
  clk: meson: a1: peripherals: determine maximum register in regmap config
parents 4cece764 11981485

drivers/clk/meson/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -30,6 +30,10 @@ config COMMON_CLK_MESON_VID_PLL_DIV 
	tristate

	select COMMON_CLK_MESON_REGMAP



config COMMON_CLK_MESON_VCLK

	tristate

	select COMMON_CLK_MESON_REGMAP



config COMMON_CLK_MESON_CLKC_UTILS

	tristate
@@ -140,6 +144,7 @@ config COMMON_CLK_G12A 
	select COMMON_CLK_MESON_EE_CLKC

	select COMMON_CLK_MESON_CPU_DYNDIV

	select COMMON_CLK_MESON_VID_PLL_DIV

	select COMMON_CLK_MESON_VCLK

	select MFD_SYSCON

	help

	  Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2

drivers/clk/meson/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o 
obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o

obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o

obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o

obj-$(CONFIG_COMMON_CLK_MESON_VCLK) += vclk.o



# Amlogic Clock controllers

drivers/clk/meson/a1-peripherals.c

+1 −0
Original line number Diff line number Diff line
@@ -2187,6 +2187,7 @@ static struct regmap_config a1_periphs_regmap_cfg = { 
	.reg_bits   = 32,

	.val_bits   = 32,

	.reg_stride = 4,

	.max_register = DMC_CLK_CTRL,

};



static struct meson_clk_hw_data a1_periphs_clks = {

drivers/clk/meson/a1-pll.c

+1 −0
Original line number Diff line number Diff line
@@ -299,6 +299,7 @@ static struct regmap_config a1_pll_regmap_cfg = { 
	.reg_bits   = 32,

	.val_bits   = 32,

	.reg_stride = 4,

	.max_register = ANACTRL_HIFIPLL_STS,

};



static struct meson_clk_hw_data a1_pll_clks = {

drivers/clk/meson/axg-aoclk.c

+1 −1
Original line number Diff line number Diff line
@@ -340,4 +340,4 @@ static struct platform_driver axg_aoclkc_driver = { 
};



module_platform_driver(axg_aoclkc_driver);

MODULE_LICENSE("GPL v2");
 
MODULE_LICENSE("GPL");