Commit d871a940 authored by Niklas Söderlund's avatar Niklas Söderlund Committed by Geert Uytterhoeven
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clk: renesas: r8a779g0: Add ISP core clocks 



Add the ISP core modules clock for Renesas R-Car V4H.

Signed-off-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250114183005.2761213-3-niklas.soderlund+renesas@ragnatech.se


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 3b0016a6

drivers/clk/renesas/r8a779g0-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -163,6 +163,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {

	DEF_MOD("isp0",		 16,	R8A779G0_CLK_S0D2_VIO),

	DEF_MOD("isp1",		 17,	R8A779G0_CLK_S0D2_VIO),

	DEF_MOD("avb0",		211,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("avb1",		212,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("avb2",		213,	R8A779G0_CLK_S0D4_HSC),