Commit d91f93c7 authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Add missing registers for dcn32 



Add missing debug registers for DCN32.

Reviewed-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 74bad61c

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

+5 −0
Original line number Diff line number Diff line
@@ -505,6 +505,8 @@ unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned 
      SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id),                                  \

      SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id),                                  \

      SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id),           \

      SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id),                                    \

      SRI_ARR(CM_TEST_DEBUG_DATA, CM, id),                                     \

      SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id),                                   \

      SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id),                        \

      SRI_ARR(CURSOR0_CONTROL, CNVC_CUR, id),                                  \
@@ -761,6 +763,7 @@ unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned 
      SRI_ARR(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),         \

      SRI_ARR(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),         \

      SRI_ARR(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),         \

      SRI_ARR(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id),                           \

      SRI_ARR(DSCCIF_CONFIG0, DSCCIF, id),                                     \

      SRI_ARR(DSCCIF_CONFIG1, DSCCIF, id),                                     \

      SRI_ARR(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)
@@ -1185,6 +1188,8 @@ unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned 
      SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),                                  \

      SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), SR(DCHUBBUB_ARB_SAT_LEVEL),            \

      SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND), SR(DCHUBBUB_GLOBAL_TIMER_CNTL),        \

      SR(DCHUBBUB_TEST_DEBUG_INDEX),                                           \

      SR(DCHUBBUB_TEST_DEBUG_DATA),                                            \

      SR(DCHUBBUB_SOFT_RESET), SR(DCHUBBUB_CRC_CTRL),                          \

      SR(DCN_VM_FB_LOCATION_BASE), SR(DCN_VM_FB_LOCATION_TOP),                 \

      SR(DCN_VM_FB_OFFSET), SR(DCN_VM_AGP_BOT), SR(DCN_VM_AGP_TOP),            \