Commit da63df07 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Add more checks for DSC / HUBP ONO guarantees 



[WHY]
For non-zero DSC instances it's possible that the HUBP domain required
to drive it for sequential ONO ASICs isn't met, potentially causing
the logic to the tile to enter an undefined state leading to a system
hang.

[HOW]
Add more checks to ensure that the HUBP domain matching the DSC instance
is appropriately powered.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarDuncan Ma <duncan.ma@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bf6003f2

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

+28 −0
Original line number Diff line number Diff line
@@ -1047,6 +1047,15 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, 
			if (dc->caps.sequential_ono) {

				update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;

				update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;



				/* All HUBP/DPP instances must be powered if the DSC inst != HUBP inst */

				if (!pipe_ctx->top_pipe && pipe_ctx->plane_res.hubp &&

				    pipe_ctx->plane_res.hubp->inst != pipe_ctx->stream_res.dsc->inst) {

					for (j = 0; j < dc->res_pool->pipe_count; ++j) {

						update_state->pg_pipe_res_update[PG_HUBP][j] = false;

						update_state->pg_pipe_res_update[PG_DPP][j] = false;

					}

				}

			}

		}
@@ -1193,6 +1202,25 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, 
		update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true;



	if (dc->caps.sequential_ono) {

		for (i = 0; i < dc->res_pool->pipe_count; i++) {

			struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];



			if (new_pipe->stream_res.dsc && !new_pipe->top_pipe &&

			    update_state->pg_pipe_res_update[PG_DSC][new_pipe->stream_res.dsc->inst]) {

				update_state->pg_pipe_res_update[PG_HUBP][new_pipe->stream_res.dsc->inst] = true;

				update_state->pg_pipe_res_update[PG_DPP][new_pipe->stream_res.dsc->inst] = true;



				/* All HUBP/DPP instances must be powered if the DSC inst != HUBP inst */

				if (new_pipe->plane_res.hubp &&

				    new_pipe->plane_res.hubp->inst != new_pipe->stream_res.dsc->inst) {

					for (j = 0; j < dc->res_pool->pipe_count; ++j) {

						update_state->pg_pipe_res_update[PG_HUBP][j] = true;

						update_state->pg_pipe_res_update[PG_DPP][j] = true;

					}

				}

			}

		}



		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {

			if (update_state->pg_pipe_res_update[PG_HUBP][i] &&

			    update_state->pg_pipe_res_update[PG_DPP][i]) {