Commit da9168d8 authored by Abel Vesa's avatar Abel Vesa Committed by Dmitry Baryshkov
Browse files

Revert "drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case" 



This reverts commit d7ec9366.

The dual-DSI dual-DSC scenario seems to be broken by this commit.

Reported-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Closes: https://lore.kernel.org/r/aUR2b3FOSisTfDFj@SoMainline.org


Signed-off-by: default avatarAbel Vesa <abel.vesa@oss.qualcomm.com>
Fixes: d7ec9366 ("drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case")
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/695550/
Link: https://lore.kernel.org/r/20251219-drm-msm-dpu-revert-quad-pipe-broken-v1-2-654b46505f84@oss.qualcomm.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent 35ab5123

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

+7 −20
Original line number Diff line number Diff line
@@ -200,7 +200,7 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc, 
		struct dpu_crtc_state *crtc_state)

{

	struct dpu_crtc_mixer *m;

	u32 crcs[CRTC_QUAD_MIXERS];

	u32 crcs[CRTC_DUAL_MIXERS];



	int rc = 0;

	int i;
@@ -1328,7 +1328,6 @@ static struct msm_display_topology dpu_crtc_get_topology( 
	struct drm_display_mode *mode = &crtc_state->adjusted_mode;

	struct msm_display_topology topology = {0};

	struct drm_encoder *drm_enc;

	u32 num_rt_intf;



	drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask)

		dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state,
@@ -1342,14 +1341,11 @@ static struct msm_display_topology dpu_crtc_get_topology( 
	 * Dual display

	 * 2 LM, 2 INTF ( Split display using 2 interfaces)

	 *

	 * If DSC is enabled, try to use 4:4:2 topology if there is enough

	 * resource. Otherwise, use 2:2:2 topology.

	 *

	 * Single display

	 * 1 LM, 1 INTF

	 * 2 LM, 1 INTF (stream merge to support high resolution interfaces)

	 *

	 * If DSC is enabled, use 2:2:1 topology

	 * If DSC is enabled, use 2 LMs for 2:2:1 topology

	 *

	 * Add dspps to the reservation requirements if ctm is requested

	 *
@@ -1361,23 +1357,14 @@ static struct msm_display_topology dpu_crtc_get_topology( 
	 * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check.

	 */



	num_rt_intf = topology.num_intf;

	if (topology.cwb_enabled)

		num_rt_intf--;



	if (topology.num_dsc) {

		if (dpu_kms->catalog->dsc_count >= num_rt_intf * 2)

			topology.num_dsc = num_rt_intf * 2;

		else

			topology.num_dsc = num_rt_intf;

		topology.num_lm = topology.num_dsc;

	} else if (num_rt_intf == 2) {

	if (topology.num_intf == 2 && !topology.cwb_enabled)

		topology.num_lm = 2;

	else if (topology.num_dsc == 2)

		topology.num_lm = 2;

	} else if (dpu_kms->catalog->caps->has_3d_merge) {

	else if (dpu_kms->catalog->caps->has_3d_merge)

		topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;

	} else {

	else

		topology.num_lm = 1;

	}



	if (crtc_state->ctm)

		topology.num_dspp = topology.num_lm;

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h

+3 −3
Original line number Diff line number Diff line
@@ -210,7 +210,7 @@ struct dpu_crtc_state { 


	bool bw_control;

	bool bw_split_vote;

	struct drm_rect lm_bounds[CRTC_QUAD_MIXERS];

	struct drm_rect lm_bounds[CRTC_DUAL_MIXERS];



	uint64_t input_fence_timeout_ns;
@@ -218,10 +218,10 @@ struct dpu_crtc_state { 


	/* HW Resources reserved for the crtc */

	u32 num_mixers;

	struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS];

	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];



	u32 num_ctls;

	struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS];

	struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];



	enum dpu_crtc_crc_source crc_source;

	int crc_frame_skip_count;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

+20 −9
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ 
#define MAX_PHYS_ENCODERS_PER_VIRTUAL \

	(MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)



#define MAX_CHANNELS_PER_ENC 4

#define MAX_CHANNELS_PER_ENC 2

#define MAX_CWB_PER_ENC 2



#define IDLE_SHORT_TIMEOUT	1
@@ -661,6 +661,7 @@ void dpu_encoder_update_topology(struct drm_encoder *drm_enc, 
	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);

	struct msm_drm_private *priv = dpu_enc->base.dev->dev_private;

	struct msm_display_info *disp_info = &dpu_enc->disp_info;

	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);

	struct drm_connector *connector;

	struct drm_connector_state *conn_state;

	struct drm_framebuffer *fb;
@@ -674,12 +675,22 @@ void dpu_encoder_update_topology(struct drm_encoder *drm_enc, 


	dsc = dpu_encoder_get_dsc_config(drm_enc);



	/* We only support 2 DSC mode (with 2 LM and 1 INTF) */

	if (dsc) {

		/*

	 * Set DSC number as 1 to mark the enabled status, will be adjusted

	 * in dpu_crtc_get_topology()

	 */

	if (dsc)

		 * Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces

		 * when Display Stream Compression (DSC) is enabled,

		 * and when enough DSC blocks are available.

		 * This is power-optimal and can drive up to (including) 4k

		 * screens.

		 */

		WARN(topology->num_intf > 2,

		     "DSC topology cannot support more than 2 interfaces\n");

		if (topology->num_intf >= 2 || dpu_kms->catalog->dsc_count >= 2)

			topology->num_dsc = 2;

		else

			topology->num_dsc = 1;

	}



	connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);

	if (!connector)
@@ -2169,8 +2180,8 @@ static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc) 
{

	int i, num_lm;

	struct dpu_global_state *global_state;

	struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];

	struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC];

	struct dpu_hw_blk *hw_lm[2];

	struct dpu_hw_mixer *hw_mixer[2];

	struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;



	/* reset all mixers for this encoder */

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

+1 −1
Original line number Diff line number Diff line
@@ -302,7 +302,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( 


	/* Use merge_3d unless DSC MERGE topology is used */

	if (phys_enc->split_role == ENC_ROLE_SOLO &&

	    (dpu_cstate->num_mixers != 1) &&

	    dpu_cstate->num_mixers == CRTC_DUAL_MIXERS &&

	    !dpu_encoder_use_dsc_merge(phys_enc->parent))

		return BLEND_3D_H_ROW_INT;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ 
#define DPU_MAX_IMG_WIDTH 0x3fff

#define DPU_MAX_IMG_HEIGHT 0x3fff



#define CRTC_QUAD_MIXERS	4

#define CRTC_DUAL_MIXERS	2



#define MAX_XIN_COUNT 16