Commit db20113d authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/rcar' 

- Add generic T_PVPERL macro for the required interval between power being
  stable and PERST# being inactive (Yoshihiro Shimoda)

- Factor out dw_pcie_link_set_max_link_width() (Yoshihiro Shimoda)

- Update PCI_EXP_LNKCAP_MLW so Link Capabilities shows the correct max link
  width (Yoshihiro Shimoda)

- Drop tegra194 PCI_EXP_LNKCAP_MLW setting since dw_pcie_setup() already
  does it (Yoshihiro Shimoda)

- Add dwc support for different dbi and dbi2 register offsets, to be used
  for R-Car Gen4 controllers (Yoshihiro Shimoda)

- Add EDMA_UNROLL capability flag for R-Car Gen4 controllers that don't
  correctly advertise unrolled mapping via their eDMA CTRL register
  (Yoshihiro Shimoda)

- Export dw_pcie_ep_exit() for use by the modular R-Car Gen4 driver
  (Yoshihiro Shimoda)

- Add .pre_init() and .deinit() hooks for use by R-Car Gen4 controllers
  (Yoshihiro Shimoda)

- Increase snps,dw-pcie DT reg and reg-names maxItems for R-Car Gen4
  controllers (Yoshihiro Shimoda)

- Add rcar-gen4-pci host and endpoint DT bindings and drivers (Yoshihiro
  Shimoda)

- Add Renesas R8A779F0 Device ID to pci_endpoint_test to allow testing on
  R-Car S4-8 (Yoshihiro Shimoda)

* pci/controller/rcar:
  misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller
  MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4
  PCI: rcar-gen4: Add endpoint mode support
  PCI: rcar-gen4: Add R-Car Gen4 PCIe controller support for host mode
  dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint
  dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host
  dt-bindings: PCI: dwc: Update maxItems of reg and reg-names
  PCI: dwc: endpoint: Introduce .pre_init() and .deinit()
  PCI: dwc: Expose dw_pcie_write_dbi2() to module
  PCI: dwc: Expose dw_pcie_ep_exit() to module
  PCI: dwc: Add EDMA_UNROLL capability flag
  PCI: dwc: endpoint: Add multiple PFs support for dbi2
  PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting
  PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling
  PCI: dwc: Add dw_pcie_link_set_max_link_width()
  PCI: Add T_PVPERL macro
parents eecffeb0 6c4b3993

Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2022-2023 Renesas Electronics Corp.

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas R-Car Gen4 PCIe Endpoint



maintainers:

  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>



allOf:

  - $ref: snps,dw-pcie-ep.yaml#



properties:

  compatible:

    items:

      - const: renesas,r8a779f0-pcie-ep   # R-Car S4-8

      - const: renesas,rcar-gen4-pcie-ep  # R-Car Gen4



  reg:

    maxItems: 7



  reg-names:

    items:

      - const: dbi

      - const: dbi2

      - const: atu

      - const: dma

      - const: app

      - const: phy

      - const: addr_space



  interrupts:

    maxItems: 3



  interrupt-names:

    items:

      - const: dma

      - const: sft_ce

      - const: app



  clocks:

    maxItems: 2



  clock-names:

    items:

      - const: core

      - const: ref



  power-domains:

    maxItems: 1



  resets:

    maxItems: 1



  reset-names:

    items:

      - const: pwr



  max-link-speed:

    maximum: 4



  num-lanes:

    maximum: 4



  max-functions:

    maximum: 2



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - interrupt-names

  - clocks

  - clock-names

  - power-domains

  - resets

  - reset-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/power/r8a779f0-sysc.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie0_ep: pcie-ep@e65d0000 {

            compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep";

            reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,

                  <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,

                  <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,

                  <0 0xfe000000 0 0x400000>;

            reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";

            interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "dma", "sft_ce", "app";

            clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;

            clock-names = "core", "ref";

            power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;

            resets = <&cpg 624>;

            reset-names = "pwr";

            max-link-speed = <4>;

            num-lanes = <2>;

            max-functions = /bits/ 8 <2>;

        };

    };

Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2022-2023 Renesas Electronics Corp.

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas R-Car Gen4 PCIe Host



maintainers:

  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>



allOf:

  - $ref: snps,dw-pcie.yaml#



properties:

  compatible:

    items:

      - const: renesas,r8a779f0-pcie   # R-Car S4-8

      - const: renesas,rcar-gen4-pcie  # R-Car Gen4



  reg:

    maxItems: 7



  reg-names:

    items:

      - const: dbi

      - const: dbi2

      - const: atu

      - const: dma

      - const: app

      - const: phy

      - const: config



  interrupts:

    maxItems: 4



  interrupt-names:

    items:

      - const: msi

      - const: dma

      - const: sft_ce

      - const: app



  clocks:

    maxItems: 2



  clock-names:

    items:

      - const: core

      - const: ref



  power-domains:

    maxItems: 1



  resets:

    maxItems: 1



  reset-names:

    items:

      - const: pwr



  max-link-speed:

    maximum: 4



  num-lanes:

    maximum: 4



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - interrupt-names

  - clocks

  - clock-names

  - power-domains

  - resets

  - reset-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/power/r8a779f0-sysc.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie: pcie@e65d0000 {

            compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie";

            reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,

                  <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,

                  <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,

                  <0 0xfe000000 0 0x400000>;

            reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";

            interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "msi", "dma", "sft_ce", "app";

            clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;

            clock-names = "core", "ref";

            power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;

            resets = <&cpg 624>;

            reset-names = "pwr";

            max-link-speed = <4>;

            num-lanes = <2>;

            #address-cells = <3>;

            #size-cells = <2>;

            bus-range = <0x00 0xff>;

            device_type = "pci";

            ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,

                     <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;

            dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

            #interrupt-cells = <1>;

            interrupt-map-mask = <0 0 0 7>;

            interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;

            snps,enable-cdm-check;

        };

    };

Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml

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@@ -33,11 +33,11 @@ properties: 
      specific for each activated function, while the rest of the sub-spaces

      are common for all of them (if there are more than one).

    minItems: 2

    maxItems: 6

    maxItems: 7



  reg-names:

    minItems: 2

    maxItems: 6

    maxItems: 7



  interrupts:

    description:

Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml

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@@ -33,11 +33,11 @@ properties: 
      normal controller functioning. iATU memory IO region is also required

      if the space is unrolled (IP-core version >= 4.80a).

    minItems: 2

    maxItems: 5

    maxItems: 7



  reg-names:

    minItems: 2

    maxItems: 5

    maxItems: 7

    items:

      oneOf:

        - description:

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

+2 −2
Original line number Diff line number Diff line
@@ -42,11 +42,11 @@ properties: 
      are required for the normal controller work. iATU memory IO region is

      also required if the space is unrolled (IP-core version >= 4.80a).

    minItems: 2

    maxItems: 5

    maxItems: 7



  reg-names:

    minItems: 2

    maxItems: 5

    maxItems: 7

    items:

      oneOf:

        - description: