Commit db2cc94f authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/keystone' 

- Enable BAR 0 only for v3.65a to avoid Completion Timeouts that
  cause a 45 second boot delay on the v4.90a-based AM654x SoC (Siddharth
  Vadapalli)

- Avoid a NULL pointer dereference if DT failed to provide a host bridge
  memory window (Aleksandr Mishin)

* pci/controller/keystone:
  PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)
  PCI: keystone: Fix NULL pointer dereference in case of DT error in ks_pcie_setup_rc_app_regs()
  PCI: keystone: Don't enable BAR 0 for AM654x
  PCI: keystone: Relocate ks_pcie_set/clear_dbi_mode()
parents 477ddcd8 86f271f2

drivers/pci/controller/dwc/pci-keystone.c

+118 −82
Original line number Diff line number Diff line
@@ -34,6 +34,11 @@ 
#define PCIE_DEVICEID_SHIFT	16



/* Application registers */

#define PID				0x000

#define RTL				GENMASK(15, 11)

#define RTL_SHIFT			11

#define AM6_PCI_PG1_RTL_VER		0x15



#define CMD_STATUS			0x004

#define LTSSM_EN_VAL		        BIT(0)

#define OB_XLAT_EN_VAL		        BIT(1)
@@ -104,6 +109,8 @@ 


#define to_keystone_pcie(x)		dev_get_drvdata((x)->dev)



#define PCI_DEVICE_ID_TI_AM654X		0xb00c



struct ks_pcie_of_data {

	enum dw_pcie_device_mode mode;

	const struct dw_pcie_host_ops *host_ops;
@@ -245,8 +252,68 @@ static struct irq_chip ks_pcie_msi_irq_chip = { 
	.irq_unmask = ks_pcie_msi_unmask,

};



/**

 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers

 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone

 *	     PCIe host controller driver information.

 *

 * Since modification of dbi_cs2 involves different clock domain, read the

 * status back to ensure the transition is complete.

 */

static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)

{

	u32 val;



	val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	val |= DBI_CS2;

	ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);



	do {

		val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	} while (!(val & DBI_CS2));

}



/**

 * ks_pcie_clear_dbi_mode() - Disable DBI mode

 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone

 *	     PCIe host controller driver information.

 *

 * Since modification of dbi_cs2 involves different clock domain, read the

 * status back to ensure the transition is complete.

 */

static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)

{

	u32 val;



	val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	val &= ~DBI_CS2;

	ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);



	do {

		val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	} while (val & DBI_CS2);

}



static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);



	/* Configure and set up BAR0 */

	ks_pcie_set_dbi_mode(ks_pcie);



	/* Enable BAR0 */

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);



	ks_pcie_clear_dbi_mode(ks_pcie);



	/*

	 * For BAR0, just setting bus address for inbound writes (MSI) should

	 * be sufficient.  Use physical address to avoid any conflicts.

	 */

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);



	pp->msi_irq_chip = &ks_pcie_msi_irq_chip;

	return dw_pcie_allocate_domains(pp);

}
@@ -340,59 +407,22 @@ static const struct irq_domain_ops ks_pcie_intx_irq_domain_ops = { 
	.xlate = irq_domain_xlate_onetwocell,

};



/**

 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers

 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone

 *	     PCIe host controller driver information.

 *

 * Since modification of dbi_cs2 involves different clock domain, read the

 * status back to ensure the transition is complete.

 */

static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)

{

	u32 val;



	val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	val |= DBI_CS2;

	ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);



	do {

		val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	} while (!(val & DBI_CS2));

}



/**

 * ks_pcie_clear_dbi_mode() - Disable DBI mode

 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone

 *	     PCIe host controller driver information.

 *

 * Since modification of dbi_cs2 involves different clock domain, read the

 * status back to ensure the transition is complete.

 */

static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)

{

	u32 val;



	val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	val &= ~DBI_CS2;

	ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);



	do {

		val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	} while (val & DBI_CS2);

}



static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)

static int ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)

{

	u32 val;

	u32 num_viewport = ks_pcie->num_viewport;

	struct dw_pcie *pci = ks_pcie->pci;

	struct dw_pcie_rp *pp = &pci->pp;

	u64 start, end;

	struct resource_entry *entry;

	struct resource *mem;

	u64 start, end;

	int i;



	mem = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM)->res;

	entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);

	if (!entry)

		return -ENODEV;



	mem = entry->res;

	start = mem->start;

	end = mem->end;
@@ -403,7 +433,7 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 
	ks_pcie_clear_dbi_mode(ks_pcie);



	if (ks_pcie->is_am6)

		return;

		return 0;



	val = ilog2(OB_WIN_SIZE);

	ks_pcie_app_writel(ks_pcie, OB_SIZE, val);
@@ -420,6 +450,8 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 
	val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);

	val |= OB_XLAT_EN_VAL;

	ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);



	return 0;

}



static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus,
@@ -445,44 +477,10 @@ static struct pci_ops ks_child_pcie_ops = { 
	.write = pci_generic_config_write,

};



/**

 * ks_pcie_v3_65_add_bus() - keystone add_bus post initialization

 * @bus: A pointer to the PCI bus structure.

 *

 * This sets BAR0 to enable inbound access for MSI_IRQ register

 */

static int ks_pcie_v3_65_add_bus(struct pci_bus *bus)

{

	struct dw_pcie_rp *pp = bus->sysdata;

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);



	if (!pci_is_root_bus(bus))

		return 0;



	/* Configure and set up BAR0 */

	ks_pcie_set_dbi_mode(ks_pcie);



	/* Enable BAR0 */

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);



	ks_pcie_clear_dbi_mode(ks_pcie);



	 /*

	  * For BAR0, just setting bus address for inbound writes (MSI) should

	  * be sufficient.  Use physical address to avoid any conflicts.

	  */

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);



	return 0;

}



static struct pci_ops ks_pcie_ops = {

	.map_bus = dw_pcie_own_conf_map_bus,

	.read = pci_generic_config_read,

	.write = pci_generic_config_write,

	.add_bus = ks_pcie_v3_65_add_bus,

};



/**
@@ -525,7 +523,11 @@ static int ks_pcie_start_link(struct dw_pcie *pci) 
static void ks_pcie_quirk(struct pci_dev *dev)

{

	struct pci_bus *bus = dev->bus;

	struct keystone_pcie *ks_pcie;

	struct device *bridge_dev;

	struct pci_dev *bridge;

	u32 val;



	static const struct pci_device_id rc_pci_devids[] = {

		{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),

		 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
@@ -537,6 +539,11 @@ static void ks_pcie_quirk(struct pci_dev *dev) 
		 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },

		{ 0, },

	};

	static const struct pci_device_id am6_pci_devids[] = {

		{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X),

		 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },

		{ 0, },

	};



	if (pci_is_root_bus(bus))

		bridge = dev;
@@ -558,10 +565,36 @@ static void ks_pcie_quirk(struct pci_dev *dev) 
	 */

	if (pci_match_id(rc_pci_devids, bridge)) {

		if (pcie_get_readrq(dev) > 256) {

			dev_info(&dev->dev, "limiting MRRS to 256\n");

			dev_info(&dev->dev, "limiting MRRS to 256 bytes\n");

			pcie_set_readrq(dev, 256);

		}

	}



	/*

	 * Memory transactions fail with PCI controller in AM654 PG1.0

	 * when MRRS is set to more than 128 bytes. Force the MRRS to

	 * 128 bytes in all downstream devices.

	 */

	if (pci_match_id(am6_pci_devids, bridge)) {

		bridge_dev = pci_get_host_bridge_device(dev);

		if (!bridge_dev && !bridge_dev->parent)

			return;



		ks_pcie = dev_get_drvdata(bridge_dev->parent);

		if (!ks_pcie)

			return;



		val = ks_pcie_app_readl(ks_pcie, PID);

		val &= RTL;

		val >>= RTL_SHIFT;

		if (val != AM6_PCI_PG1_RTL_VER)

			return;



		if (pcie_get_readrq(dev) > 128) {

			dev_info(&dev->dev, "limiting MRRS to 128 bytes\n");

			pcie_set_readrq(dev, 128);

		}

	}

}

DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk);
@@ -814,7 +847,10 @@ static int __init ks_pcie_host_init(struct dw_pcie_rp *pp) 
		return ret;



	ks_pcie_stop_link(pci);

	ks_pcie_setup_rc_app_regs(ks_pcie);

	ret = ks_pcie_setup_rc_app_regs(ks_pcie);

	if (ret)

		return ret;



	writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),

			pci->dbi_base + PCI_IO_BASE);