Commit db4a4086 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

x86/apic: Use u32 for wakeup_secondary_cpu[_64]() 



APIC IDs are used with random data types u16, u32, int, unsigned int,
unsigned long.

Make it all consistently use u32 because that reflects the hardware
register width.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Tested-by: default avatarJuergen Gross <jgross@suse.com>
Tested-by: default avatarSohil Mehta <sohil.mehta@intel.com>
Tested-by: default avatarMichael Kelley <mikelley@microsoft.com>
Tested-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: default avatarZhang Rui <rui.zhang@intel.com>
Reviewed-by: default avatarArjan van de Ven <arjan@linux.intel.com>
Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20230814085113.233274223@linutronix.de
parent 59f7928c

arch/x86/hyperv/hv_vtl.c

+1 −1
Original line number Diff line number Diff line
@@ -196,7 +196,7 @@ static int hv_vtl_apicid_to_vp_id(u32 apic_id) 
	return ret;

}



static int hv_vtl_wakeup_secondary_cpu(int apicid, unsigned long start_eip)

static int hv_vtl_wakeup_secondary_cpu(u32 apicid, unsigned long start_eip)

{

	int vp_id;

arch/x86/include/asm/apic.h

+4 −4
Original line number Diff line number Diff line
@@ -302,9 +302,9 @@ struct apic { 
	u32	(*set_apic_id)(u32 apicid);



	/* wakeup_secondary_cpu */

	int	(*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);

	int	(*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip);

	/* wakeup secondary CPU using 64-bit wakeup point */

	int	(*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip);

	int	(*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip);



	char	*name;

};
@@ -322,8 +322,8 @@ struct apic_override { 
	void	(*send_IPI_self)(int vector);

	u64	(*icr_read)(void);

	void	(*icr_write)(u32 low, u32 high);

	int	(*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);

	int	(*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip);

	int	(*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip);

	int	(*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip);

};



/*

arch/x86/kernel/acpi/boot.c

+1 −1
Original line number Diff line number Diff line
@@ -359,7 +359,7 @@ acpi_parse_lapic_nmi(union acpi_subtable_headers * header, const unsigned long e 
}



#ifdef CONFIG_X86_64

static int acpi_wakeup_cpu(int apicid, unsigned long start_ip)

static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip)

{

	/*

	 * Remap mailbox memory only for the first call to acpi_wakeup_cpu().

arch/x86/kernel/apic/apic_noop.c

+1 −1
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ static void noop_send_IPI_allbutself(int vector) { } 
static void noop_send_IPI_all(int vector) { }

static void noop_send_IPI_self(int vector) { }

static void noop_apic_icr_write(u32 low, u32 id) { }

static int noop_wakeup_secondary_cpu(int apicid, unsigned long start_eip) { return -1; }

static int noop_wakeup_secondary_cpu(u32 apicid, unsigned long start_eip) { return -1; }

static u64 noop_apic_icr_read(void) { return 0; }

static u32 noop_phys_pkg_id(u32 cpuid_apic, int index_msb) { return 0; }

static u32 noop_get_apic_id(u32 apicid) { return 0; }

arch/x86/kernel/apic/apic_numachip.c

+1 −1
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ static void numachip2_apic_icr_write(int apicid, unsigned int val) 
	numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val);

}



static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)

static int numachip_wakeup_secondary(u32 phys_apicid, unsigned long start_rip)

{

	numachip_apic_icr_write(phys_apicid, APIC_DM_INIT);

	numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP |