Commit dbab6356 authored by Ma Jun's avatar Ma Jun Committed by Alex Deucher
Browse files

drm/amdgpu: Optimize the asic type fix code 



Use a new struct array to define the asic information which
asic type needs to be fixed.

Signed-off-by: default avatarMa Jun <Jun.Ma2@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 36e7ff5c

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+26 −9
Original line number Diff line number Diff line
@@ -2041,6 +2041,14 @@ static const struct pci_device_id pciidlist[] = { 


MODULE_DEVICE_TABLE(pci, pciidlist);



static const struct amdgpu_asic_type_quirk asic_type_quirks[] = {

	/* differentiate between P10 and P11 asics with the same DID */

	{0x67FF, 0xE3, CHIP_POLARIS10},

	{0x67FF, 0xE7, CHIP_POLARIS10},

	{0x67FF, 0xF3, CHIP_POLARIS10},

	{0x67FF, 0xF7, CHIP_POLARIS10},

};



static const struct drm_driver amdgpu_kms_driver;



static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
@@ -2083,6 +2091,22 @@ static void amdgpu_init_debug_options(struct amdgpu_device *adev) 
	}

}



static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) {

		if (pdev->device == asic_type_quirks[i].device &&

			pdev->revision == asic_type_quirks[i].revision) {

				flags &= ~AMD_ASIC_MASK;

				flags |= asic_type_quirks[i].type;

				break;

			}

	}



	return flags;

}



static int amdgpu_pci_probe(struct pci_dev *pdev,

			    const struct pci_device_id *ent)

{
@@ -2110,15 +2134,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, 
			 "See modparam exp_hw_support\n");

		return -ENODEV;

	}

	/* differentiate between P10 and P11 asics with the same DID */

	if (pdev->device == 0x67FF &&

	    (pdev->revision == 0xE3 ||

	     pdev->revision == 0xE7 ||

	     pdev->revision == 0xF3 ||

	     pdev->revision == 0xF7)) {

		flags &= ~AMD_ASIC_MASK;

		flags |= CHIP_POLARIS10;

	}



	flags = amdgpu_fix_asic_type(pdev, flags);



	/* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,

	 * however, SME requires an indirect IOMMU mapping because the encryption

include/drm/amd_asic_type.h

+5 −0
Original line number Diff line number Diff line
@@ -68,4 +68,9 @@ enum amd_asic_type { 


extern const char *amdgpu_asic_name[];



struct amdgpu_asic_type_quirk {

	unsigned short device;	/* PCI device ID */

	u8 revision;	/* revision ID */

	unsigned short type;	/* real ASIC type */

};

#endif /*__AMD_ASIC_TYPE_H__ */