Unverified Commit dc2f2a9d authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Krzysztof Wilczyński
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PCI: qcom-ep: Use PCIE_SPEED2MBS_ENC() macro for encoding link speed 



Instead of hardcoding the link speed in MBps, use existing
PCIE_SPEED2MBS_ENC() macro that does the encoding of the link speed for
us. Also, let's Wrap it with QCOM_PCIE_LINK_SPEED_TO_BW() macro to do
the conversion to ICC speed.

This eliminates the need for a switch case in qcom_pcie_icc_update() and
also works for future Gen speeds without any code modifications.

Suggested-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/linux-pci/20231004164430.39662-2-manivannan.sadhasivam@linaro.org


Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
parent 8da2e9af

drivers/pci/controller/dwc/pcie-qcom-ep.c

+6 −25
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include <linux/reset.h>

#include <linux/module.h>



#include "../../pci.h"

#include "pcie-designware.h"



/* PARF registers */
@@ -135,10 +136,8 @@ 
#define CORE_RESET_TIME_US_MAX			1005

#define WAKE_DELAY_US				2000 /* 2 ms */



#define PCIE_GEN1_BW_MBPS			250

#define PCIE_GEN2_BW_MBPS			500

#define PCIE_GEN3_BW_MBPS			985

#define PCIE_GEN4_BW_MBPS			1969

#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \

		Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]))



#define to_pcie_ep(x)				dev_get_drvdata((x)->dev)
@@ -266,7 +265,7 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) 
static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)

{

	struct dw_pcie *pci = &pcie_ep->pci;

	u32 offset, status, bw;

	u32 offset, status;

	int speed, width;

	int ret;
@@ -279,25 +278,7 @@ static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) 
	speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);

	width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);



	switch (speed) {

	case 1:

		bw = MBps_to_icc(PCIE_GEN1_BW_MBPS);

		break;

	case 2:

		bw = MBps_to_icc(PCIE_GEN2_BW_MBPS);

		break;

	case 3:

		bw = MBps_to_icc(PCIE_GEN3_BW_MBPS);

		break;

	default:

		dev_warn(pci->dev, "using default GEN4 bandwidth\n");

		fallthrough;

	case 4:

		bw = MBps_to_icc(PCIE_GEN4_BW_MBPS);

		break;

	}



	ret = icc_set_bw(pcie_ep->icc_mem, 0, width * bw);

	ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));

	if (ret)

		dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",

			ret);
@@ -335,7 +316,7 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) 
	 * Set an initial peak bandwidth corresponding to single-lane Gen 1

	 * for the pcie-mem path.

	 */

	ret = icc_set_bw(pcie_ep->icc_mem, 0, MBps_to_icc(PCIE_GEN1_BW_MBPS));

	ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));

	if (ret) {

		dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",

			ret);