Commit dc7a06b0 authored by Nicolas Belin's avatar Nicolas Belin Committed by Linus Walleij
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pinctrl: meson-gxl: fix GPIOX sdio pins 



In the gxl driver, the sdio cmd and clk pins are inverted. It has not caused
any issue so far because devices using these pins always take both pins
so the resulting configuration is OK.

Fixes: 0f15f500 ("pinctrl: meson: Add GXL pinctrl definitions")
Reviewed-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: default avatarNicolas Belin <nbelin@baylibre.com>
Link: https://lore.kernel.org/r/1582204512-7582-1-git-send-email-nbelin@baylibre.com


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent bb6d3fb3

drivers/pinctrl/meson/pinctrl-meson-gxl.c

+2 −2
Original line number Diff line number Diff line
@@ -147,8 +147,8 @@ static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; 
static const unsigned int sdio_d1_pins[]	= { GPIOX_1 };

static const unsigned int sdio_d2_pins[]	= { GPIOX_2 };

static const unsigned int sdio_d3_pins[]	= { GPIOX_3 };

static const unsigned int sdio_cmd_pins[]	= { GPIOX_4 };

static const unsigned int sdio_clk_pins[]	= { GPIOX_5 };

static const unsigned int sdio_clk_pins[]	= { GPIOX_4 };

static const unsigned int sdio_cmd_pins[]	= { GPIOX_5 };

static const unsigned int sdio_irq_pins[]	= { GPIOX_7 };



static const unsigned int nand_ce0_pins[]	= { BOOT_8 };