Commit dcd68326 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'devicetree-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull devicetree updates from Rob Herring:

 - Convert /reserved-memory bindings to schemas

 - Convert a bunch of NFC bindings to schemas

 - Convert bindings to schema: Xilinx USB, Freescale DDR controller, Arm
   CCI-400, UBlox Neo-6M, 1-Wire GPIO, MSI controller, ASpeed LPC, OMAP
   and Inside-Secure HWRNG, register-bit-led, OV5640, Silead GSL1680,
   Elan ekth3000, Marvell bluetooth, TI wlcore, TI bluetooth, ESP
   ESP8089, tlm,trusted-foundations, Microchip cap11xx, Ralink SoCs and
   boards, and TI sysc

 - New binding schemas for: msi-ranges, Aspeed UART routing controller,
   palmbus, Xylon LogiCVC display controller, Mediatek's MT7621 SDRAM
   memory controller, and Apple M1 PCIe host

 - Run schema checks for %.dtb targets

 - Improve build time when using DT_SCHEMA_FILES

 - Improve error message when dtschema is not found

 - Various doc reference fixes in MAINTAINERS

 - Convert architectures to common CPU h/w ID parsing function
   of_get_cpu_hwid().

 - Allow for empty NUMA node IDs which may be hotplugged

 - Cleanup of __fdt_scan_reserved_mem()

 - Constify device_node parameters

 - Update dtc to upstream v1.6.1-19-g0a3a9d3449c8. Adds new checks
   'node_name_vs_property_name' and 'interrupt_map'.

 - Enable dtc 'unit_address_format' warning by default

 - Fix unittest EXPECT text for gpio hog errors

* tag 'devicetree-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (97 commits)
  dt-bindings: net: ti,bluetooth: Document default max-speed
  dt-bindings: pci: rcar-pci-ep: Document r8a7795
  dt-bindings: net: qcom,ipa: IPA does support up to two iommus
  of/fdt: Remove of_scan_flat_dt() usage for __fdt_scan_reserved_mem()
  of: unittest: document intentional interrupt-map provider build warning
  of: unittest: fix EXPECT text for gpio hog errors
  of/unittest: Disable new dtc node_name_vs_property_name and interrupt_map warnings
  scripts/dtc: Update to upstream version v1.6.1-19-g0a3a9d3449c8
  dt-bindings: arm: firmware: tlm,trusted-foundations: Convert txt bindings to yaml
  dt-bindings: display: tilcd: Fix endpoint addressing in example
  dt-bindings: input: microchip,cap11xx: Convert txt bindings to yaml
  dt-bindings: ufs: exynos-ufs: add exynosautov9 compatible
  dt-bindings: ufs: exynos-ufs: add io-coherency property
  dt-bindings: mips: convert Ralink SoCs and boards to schema
  dt-bindings: display: xilinx: Fix example with psgtr
  dt-bindings: net: nfc: nxp,pn544: Convert txt bindings to yaml
  dt-bindings: Add a help message when dtschema tools are missing
  dt-bindings: bus: ti-sysc: Update to use yaml binding
  dt-bindings: sram: Allow numbers in sram region node name
  dt-bindings: display: Document the Xylon LogiCVC display controller
  ...
parents 624ad333 4c7a7d50

Documentation/admin-guide/ramoops.rst

+1 −1
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ Setting the ramoops parameters can be done in several different manners: 
	mem=128M ramoops.mem_address=0x8000000 ramoops.ecc=1



 B. Use Device Tree bindings, as described in

 ``Documentation/devicetree/bindings/reserved-memory/ramoops.txt``.

 ``Documentation/devicetree/bindings/reserved-memory/ramoops.yaml``.

 For example::



	reserved-memory {

Documentation/devicetree/bindings/Makefile

+16 −4
Original line number Diff line number Diff line
@@ -9,6 +9,11 @@ DT_SCHEMA_MIN_VERSION = 2021.2.1 


PHONY += check_dtschema_version

check_dtschema_version:

	@which $(DT_DOC_CHECKER) >/dev/null || \

		{ echo "Error: '$(DT_DOC_CHECKER)' not found!" >&2; \

		  echo "Ensure dtschema python package is installed and in your PATH." >&2; \

		  echo "Current PATH is:" >&2; \

		  echo "$$PATH" >&2; false; }

	@{ echo $(DT_SCHEMA_MIN_VERSION); \

	$(DT_DOC_CHECKER) --version 2>/dev/null || echo 0; } | sort -Vc >/dev/null || \

	{ echo "ERROR: dtschema minimum version is v$(DT_SCHEMA_MIN_VERSION)" >&2; false; }
@@ -22,13 +27,20 @@ $(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE 
# Use full schemas when checking %.example.dts

DT_TMP_SCHEMA := $(obj)/processed-schema-examples.json



find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \

find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \

		-name 'processed-schema*' ! \

		-name '*.example.dt.yaml' \)



ifeq ($(DT_SCHEMA_FILES),)

find_cmd = $(find_all_cmd)

else

find_cmd = echo $(addprefix $(srctree)/, $(DT_SCHEMA_FILES))

endif



quiet_cmd_yamllint = LINT    $(src)

      cmd_yamllint = ($(find_cmd) | \

                     xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true

                     xargs -n200 -P$$(nproc) \

		     $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true



quiet_cmd_chk_bindings = CHKDT   $@

      cmd_chk_bindings = ($(find_cmd) | \
@@ -38,7 +50,7 @@ quiet_cmd_mk_schema = SCHEMA $@ 
      cmd_mk_schema = f=$$(mktemp) ; \

                      $(if $(DT_MK_SCHEMA_FLAGS), \

                           printf '%s\n' $(real-prereqs), \

                           $(find_cmd)) > $$f ; \

                           $(find_all_cmd)) > $$f ; \

                      $(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \

		      rm -f $$f
@@ -48,7 +60,7 @@ define rule_chkdt 
	$(call cmd,mk_schema)

endef



DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_cmd)))

DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd)))



override DTC_FLAGS := \

	-Wno-avoid_unnecessary_addr_size \

Documentation/devicetree/bindings/arm/arm,cci-400.yaml

0 → 100644
+216 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ARM CCI Cache Coherent Interconnect Device Tree Binding



maintainers:

  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>



description: >

  ARM multi-cluster systems maintain intra-cluster coherency through a cache

  coherent interconnect (CCI) that is capable of monitoring bus transactions

  and manage coherency, TLB invalidations and memory barriers.



  It allows snooping and distributed virtual memory message broadcast across

  clusters, through memory mapped interface, with a global control register

  space and multiple sets of interface control registers, one per slave

  interface.



properties:

  $nodename:

    pattern: "^cci(@[0-9a-f]+)?$"



  compatible:

    enum:

      - arm,cci-400

      - arm,cci-500

      - arm,cci-550



  reg:

    maxItems: 1

    description: >

      Specifies base physical address of CCI control registers common to all

      interfaces.



  "#address-cells": true

  "#size-cells": true

  ranges: true



patternProperties:

  "^slave-if@[0-9a-f]+$":

    type: object



    properties:

      compatible:

        const: arm,cci-400-ctrl-if



      interface-type:

        enum:

          - ace

          - ace-lite



      reg:

        maxItems: 1



    required:

      - compatible

      - interface-type

      - reg



    additionalProperties: false



  "^pmu@[0-9a-f]+$":

    type: object



    properties:

      compatible:

        oneOf:

          - const: arm,cci-400-pmu,r0

          - const: arm,cci-400-pmu,r1

          - const: arm,cci-400-pmu

            deprecated: true

            description: >

              Permitted only where OS has secure access to CCI registers

          - const: arm,cci-500-pmu,r0

          - const: arm,cci-550-pmu,r0



      interrupts:

        minItems: 1

        maxItems: 8

        description: >

          List of counter overflow interrupts, one per counter. The interrupts

          must be specified starting with the cycle counter overflow interrupt,

          followed by counter0 overflow interrupt, counter1 overflow

          interrupt,...  ,counterN overflow interrupt.



          The CCI PMU has an interrupt signal for each counter. The number of

          interrupts must be equal to the number of counters.



      reg:

        maxItems: 1



    required:

      - compatible

      - interrupts

      - reg



    additionalProperties: false



required:

  - "#address-cells"

  - "#size-cells"

  - compatible

  - ranges

  - reg



additionalProperties: false



examples:

  - |

      / {

          #address-cells = <2>;

          #size-cells = <2>;



          compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";

          model = "V2P-CA15_CA7";

          arm,hbi = <0x249>;

          interrupt-parent = <&gic>;



          /*

           * This CCI node corresponds to a CCI component whose control

           * registers sits at address 0x000000002c090000.

           *

           * CCI slave interface @0x000000002c091000 is connected to dma

           * controller dma0.

           *

           * CCI slave interface @0x000000002c094000 is connected to CPUs

           * {CPU0, CPU1};

           *

           * CCI slave interface @0x000000002c095000 is connected to CPUs

           * {CPU2, CPU3};

           */



          cpus {

              #size-cells = <0>;

              #address-cells = <1>;



              CPU0: cpu@0 {

                  device_type = "cpu";

                  compatible = "arm,cortex-a15";

                  cci-control-port = <&cci_control1>;

                  reg = <0x0>;

              };



              CPU1: cpu@1 {

                  device_type = "cpu";

                  compatible = "arm,cortex-a15";

                  cci-control-port = <&cci_control1>;

                  reg = <0x1>;

              };



              CPU2: cpu@100 {

                  device_type = "cpu";

                  compatible = "arm,cortex-a7";

                  cci-control-port = <&cci_control2>;

                  reg = <0x100>;

              };



              CPU3: cpu@101 {

                  device_type = "cpu";

                  compatible = "arm,cortex-a7";

                  cci-control-port = <&cci_control2>;

                  reg = <0x101>;

              };

          };



          dma0: dma@3000000 {

              /* compatible = "arm,pl330", "arm,primecell"; */

              cci-control-port = <&cci_control0>;

              reg = <0x0 0x3000000 0x0 0x1000>;

              interrupts = <10>;

              #dma-cells = <1>;

              #dma-channels = <8>;

              #dma-requests = <32>;

          };



          cci@2c090000 {

              compatible = "arm,cci-400";

              #address-cells = <1>;

              #size-cells = <1>;

              reg = <0x0 0x2c090000 0 0x1000>;

              ranges = <0x0 0x0 0x2c090000 0x10000>;



              cci_control0: slave-if@1000 {

                  compatible = "arm,cci-400-ctrl-if";

                  interface-type = "ace-lite";

                  reg = <0x1000 0x1000>;

              };



              cci_control1: slave-if@4000 {

                  compatible = "arm,cci-400-ctrl-if";

                  interface-type = "ace";

                  reg = <0x4000 0x1000>;

              };



              cci_control2: slave-if@5000 {

                  compatible = "arm,cci-400-ctrl-if";

                  interface-type = "ace";

                  reg = <0x5000 0x1000>;

              };



              pmu@9000 {

                  compatible = "arm,cci-400-pmu";

                  reg = <0x9000 0x5000>;

                  interrupts = <0 101 4>,

                    <0 102 4>,

                    <0 103 4>,

                    <0 104 4>,

                    <0 105 4>;

              };

          };

      };



...

Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml

+27 −19
Original line number Diff line number Diff line
@@ -119,22 +119,6 @@ properties: 
          - const: arm,foundation-aarch64

          - const: arm,vexpress



  arm,hbi:

    $ref: '/schemas/types.yaml#/definitions/uint32'

    description: This indicates the ARM HBI (Hardware Board ID), this is

      ARM's unique board model ID, visible on the PCB's silkscreen.



  arm,vexpress,site:

    description: As Versatile Express can be configured in number of physically

      different setups, the device tree should describe platform topology.

      For this reason the root node and main motherboard node must define this

      property, describing the physical location of the children nodes.

      0 means motherboard site, while 1 and 2 are daughterboard sites, and

      0xf means "sisterboard" which is the site containing the main CPU tile.

    $ref: '/schemas/types.yaml#/definitions/uint32'

    minimum: 0

    maximum: 15



  arm,vexpress,position:

    description: When daughterboards are stacked on one site, their position

      in the stack be be described this attribute.
@@ -154,9 +138,9 @@ patternProperties: 
    description: Static Memory Bus (SMB) node, if this exists it describes

      the connection between the motherboard and any tiles. Sometimes the

      compatible is placed directly under this node, sometimes it is placed

      in a subnode named "motherboard". Sometimes the compatible includes

      in a subnode named "motherboard-bus". Sometimes the compatible includes

      "arm,vexpress,v2?-p1" sometimes (on software models) is is just

      "simple-bus". If the compatible is placed in the "motherboard" node,

      "simple-bus". If the compatible is placed in the "motherboard-bus" node,

      it is stricter and always has two compatibles.

    type: object

    $ref: '/schemas/simple-bus.yaml'
@@ -170,7 +154,9 @@ patternProperties: 
                  - arm,vexpress,v2p-p1

              - const: simple-bus

          - const: simple-bus

      motherboard:



    patternProperties:

      '^motherboard-bus@':

        type: object

        description: The motherboard description provides a single "motherboard"

          node using 2 address cells corresponding to the Static Memory Bus
@@ -183,6 +169,8 @@ patternProperties: 
            const: 2

          "#size-cells":

            const: 1

          ranges: true



          compatible:

            items:

              - enum:
@@ -196,8 +184,28 @@ patternProperties: 
              - rs1

              - rs2



          arm,hbi:

            $ref: '/schemas/types.yaml#/definitions/uint32'

            description: This indicates the ARM HBI (Hardware Board ID), this is

              ARM's unique board model ID, visible on the PCB's silkscreen.



          arm,vexpress,site:

            description: As Versatile Express can be configured in number of physically

              different setups, the device tree should describe platform topology.

              For this reason the root node and main motherboard node must define this

              property, describing the physical location of the children nodes.

              0 means motherboard site, while 1 and 2 are daughterboard sites, and

              0xf means "sisterboard" which is the site containing the main CPU tile.

            $ref: '/schemas/types.yaml#/definitions/uint32'

            minimum: 0

            maximum: 15



        required:

          - compatible



        additionalProperties:

          type: object



    required:

      - compatible

Documentation/devicetree/bindings/arm/cci-control-port.yaml

0 → 100644
+38 −0
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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/cci-control-port.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: CCI Interconnect Bus Masters binding



maintainers:

  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>



description: |

  Masters in the device tree connected to a CCI port (inclusive of CPUs

  and their cpu nodes).



select: true



properties:

  cci-control-port:

    $ref: /schemas/types.yaml#/definitions/phandle



additionalProperties: true



examples:

  - |

    cpus {

        #address-cells = <1>;

        #size-cells = <0>;



        cpu@0 {

            compatible = "arm,cortex-a15";

            device_type = "cpu";

            cci-control-port = <&cci_control1>;

            reg = <0>;

        };

    };



...