Commit dcf55829 authored by Krzysztof Karas's avatar Krzysztof Karas Committed by Andi Shyti
Browse files

drm/i915: Move out engine related macros from i915_drv.h 



Move macros related to engines out of i915_drv.h header and
place them in intel_engine.h.

Signed-off-by: default avatarKrzysztof Karas <krzysztof.karas@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://lore.kernel.org/r/9b9ed5bbdb37470fa679c5baf961424c9cfbad11.1750251040.git.krzysztof.karas@intel.com
parent c3711610

drivers/gpu/drm/i915/gt/intel_engine.h

+31 −0
Original line number Diff line number Diff line
@@ -79,6 +79,29 @@ struct lock_class_key; 
#define ENGINE_WRITE(...)	__ENGINE_WRITE_OP(write, __VA_ARGS__)

#define ENGINE_WRITE_FW(...)	__ENGINE_WRITE_OP(write_fw, __VA_ARGS__)



#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))

#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)



#define __ENGINE_INSTANCES_MASK(mask, first, count) ({			\

	unsigned int first__ = (first);					\

	unsigned int count__ = (count);					\

	((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__;	\

})



#define ENGINE_INSTANCES_MASK(gt, first, count) \

	__ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)



#define RCS_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)

#define BCS_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)

#define VDBOX_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)

#define VEBOX_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)

#define CCS_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)



#define GEN6_RING_FAULT_REG_READ(engine__) \

	intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
@@ -355,4 +378,12 @@ u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value); 
u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value);

u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value);



#define rb_to_uabi_engine(rb) \

	rb_entry_safe(rb, struct intel_engine_cs, uabi_node)



#define for_each_uabi_engine(engine__, i915__) \

	for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\

	     (engine__); \

	     (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))



#endif /* _INTEL_RINGBUFFER_H_ */

drivers/gpu/drm/i915/i915_drv.h

+0 −31
Original line number Diff line number Diff line
@@ -374,14 +374,6 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) 
	return i915->gt[0];

}



#define rb_to_uabi_engine(rb) \

	rb_entry_safe(rb, struct intel_engine_cs, uabi_node)



#define for_each_uabi_engine(engine__, i915__) \

	for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\

	     (engine__); \

	     (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))



#define INTEL_INFO(i915)	((i915)->__info)

#define RUNTIME_INFO(i915)	(&(i915)->__runtime)

#define DRIVER_CAPS(i915)	(&(i915)->caps)
@@ -590,29 +582,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 
#define IS_GEN9_LP(i915)	(IS_BROXTON(i915) || IS_GEMINILAKE(i915))

#define IS_GEN9_BC(i915)	(GRAPHICS_VER(i915) == 9 && !IS_GEN9_LP(i915))



#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))

#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)



#define __ENGINE_INSTANCES_MASK(mask, first, count) ({			\

	unsigned int first__ = (first);					\

	unsigned int count__ = (count);					\

	((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__;	\

})



#define ENGINE_INSTANCES_MASK(gt, first, count) \

	__ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)



#define RCS_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)

#define BCS_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)

#define VDBOX_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)

#define VEBOX_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)

#define CCS_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)



#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)



/*