Commit dd1bd5bf authored by Komal Bajaj's avatar Komal Bajaj Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: qdu1000: Add USB3 and PHY support 



Add devicetree nodes for enabling USB3 controller, Qcom QMP PHY and
SNPS HS PHY on QDU1000/QRU1000 SoCs. Also add required pins for USB,
so that the interface can work reliably.

Co-developed-by: default avatarAmrit Anand <quic_amrianan@quicinc.com>
Signed-off-by: default avatarAmrit Anand <quic_amrianan@quicinc.com>
Signed-off-by: default avatarKomal Bajaj <quic_kbajaj@quicinc.com>
Link: https://lore.kernel.org/r/20240502090326.21489-2-quic_kbajaj@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent c1aefeae

arch/arm64/boot/dts/qcom/qdu1000.dtsi

+120 −0
Original line number Diff line number Diff line
@@ -6,6 +6,8 @@ 
#include <dt-bindings/clock/qcom,qdu1000-gcc.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/dma/qcom-gpi.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interconnect/qcom,icc.h>

#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/power/qcom-rpmpd.h>
@@ -913,6 +915,124 @@ opp-384000000 { 
			};

		};



		usb_1_hsphy: phy@88e3000 {

			compatible = "qcom,qdu1000-usb-hs-phy",

				     "qcom,usb-snps-hs-7nm-phy";

			reg = <0x0 0x088e3000 0x0 0x120>;

			#phy-cells = <0>;



			clocks =<&gcc GCC_USB2_CLKREF_EN>;

			clock-names = "ref";



			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;



			status = "disabled";

		};



		usb_1_qmpphy: phy@88e5000 {

			compatible = "qcom,qdu1000-qmp-usb3-uni-phy";

			reg = <0x0 0x088e5000 0x0 0x2000>;



			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

				 <&gcc GCC_USB2_CLKREF_EN>,

				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,

				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

			clock-names = "aux",

				      "ref",

				      "com_aux",

				      "pipe";



			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,

				 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;

			reset-names = "phy",

				      "phy_phy";



			#clock-cells = <0>;

			clock-output-names = "usb3_uni_phy_pipe_clk_src";



			#phy-cells = <0>;



			status = "disabled";

		};



		usb_1: usb@a6f8800 {

			compatible = "qcom,qdu1000-dwc3", "qcom,dwc3";

			reg = <0 0x0a6f8800 0 0x400>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,

				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,

				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,

				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;

			clock-names = "cfg_noc",

				      "core",

				      "sleep",

				      "mock_utmi";



			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,

					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;

			assigned-clock-rates = <19200000>, <200000000>;



			interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 8 IRQ_TYPE_EDGE_RISING>,

					      <&pdc 9 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "hs_phy_irq",

					  "ss_phy_irq",

					  "dp_hs_phy_irq",

					  "dm_hs_phy_irq";



			power-domains = <&gcc USB30_PRIM_GDSC>;

			required-opps = <&rpmhpd_opp_nom>;



			resets = <&gcc GCC_USB30_PRIM_BCR>;



			interconnects = <&system_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS

					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,

					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

					 &system_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>;



			interconnect-names = "usb-ddr",

					     "apps-usb";



			status = "disabled";



			usb_1_dwc3: usb@a600000 {

				compatible = "snps,dwc3";

				reg = <0 0x0a600000 0 0xcd00>;

				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;



				iommus = <&apps_smmu 0xc0 0x0>;

				snps,dis_u2_susphy_quirk;

				snps,dis_enblslpm_quirk;

				phys = <&usb_1_hsphy>,

				       <&usb_1_qmpphy>;

				phy-names = "usb2-phy",

					    "usb3-phy";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						usb_1_dwc3_hs: endpoint {

						};

					};



					port@1 {

						reg = <1>;



						usb_1_dwc3_ss: endpoint {

						};

					};

				};

			};

		};



		pdc: interrupt-controller@b220000 {

			compatible = "qcom,qdu1000-pdc", "qcom,pdc";

			reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;