Commit dd22f444 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/errata' into for-next/core 

* for-next/errata:
  arm64: errata: Enable the AC03_CPU_38 workaround for ampere1a
parents d2ea6380 db0d8a84

Documentation/arch/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -55,6 +55,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Ampere         | AmpereOne       | AC03_CPU_38     | AMPERE_ERRATUM_AC03_CPU_38  |

+----------------+-----------------+-----------------+-----------------------------+

| Ampere         | AmpereOne AC04  | AC04_CPU_10     | AMPERE_ERRATUM_AC03_CPU_38  |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2457168        | ARM64_ERRATUM_2457168       |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+1 −1
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@@ -423,7 +423,7 @@ config AMPERE_ERRATUM_AC03_CPU_38 
	default y

	help

	  This option adds an alternative code sequence to work around Ampere

	  erratum AC03_CPU_38 on AmpereOne.

	  errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne.



	  The affected design reports FEAT_HAFDBS as not implemented in

	  ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -143,6 +143,7 @@ 
#define APPLE_CPU_PART_M2_AVALANCHE_MAX	0x039



#define AMPERE_CPU_PART_AMPERE1		0xAC3

#define AMPERE_CPU_PART_AMPERE1A	0xAC4



#define MICROSOFT_CPU_PART_AZURE_COBALT_100	0xD49 /* Based on r0p0 of ARM Neoverse N2 */
@@ -212,6 +213,7 @@ 
#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)

#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)

#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)

#define MIDR_AMPERE1A MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1A)

#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)



/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */

arch/arm64/kernel/cpu_errata.c

+9 −1
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@@ -456,6 +456,14 @@ static const struct midr_range erratum_spec_ssbs_list[] = { 
};

#endif



#ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38

static const struct midr_range erratum_ac03_cpu_38_list[] = {

	MIDR_ALL_VERSIONS(MIDR_AMPERE1),

	MIDR_ALL_VERSIONS(MIDR_AMPERE1A),

	{},

};

#endif



const struct arm64_cpu_capabilities arm64_errata[] = {

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE

	{
@@ -772,7 +780,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
	{

		.desc = "AmpereOne erratum AC03_CPU_38",

		.capability = ARM64_WORKAROUND_AMPERE_AC03_CPU_38,

		ERRATA_MIDR_ALL_VERSIONS(MIDR_AMPERE1),

		ERRATA_MIDR_RANGE_LIST(erratum_ac03_cpu_38_list),

	},

#endif

	{