Commit dd249a16 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/{i915, xe}/reg: rename masked field helpers REG_MASKED_FIELD*() 



The underscore prefixed masked field helper names aren't great. Rename
them REG_MASKED_FIELD(), REG_MASKED_FIELD_ENABLE(), and
REG_MASKED_FIELD_DISABLE(). This is more in line with the existing
REG_FIELD_PREP() etc. helpers, and using "field" instead of "bit" is
more accurate for the functionality.

This is done with:

sed -i 's/_MASKED_FIELD/REG_MASKED_FIELD/g' $(git grep -wl _MASKED_FIELD)
sed -i 's/_MASKED_BIT_ENABLE/REG_MASKED_FIELD_ENABLE/g' $(git grep -wl _MASKED_BIT_ENABLE)
sed -i 's/_MASKED_BIT_DISABLE/REG_MASKED_FIELD_DISABLE/g' $(git grep -wl _MASKED_BIT_DISABLE)

with some manual indentation fixes on top.

Reviewed-by: default avatarMichał Grzelak <michal.grzelak@intel.com>
Acked-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/49dc20448a12f3e03f5f8347540d167a281b8987.1772042022.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent fa3fe9d9

drivers/gpu/drm/i915/display/i9xx_wm.c

+4 −4
Original line number Diff line number Diff line
@@ -182,8 +182,8 @@ static bool _intel_set_memory_cxsr(struct intel_display *display, bool enable) 
		intel_de_posting_read(display, DSPFW3(display));

	} else if (display->platform.i945g || display->platform.i945gm) {

		was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

		val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :

			       _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);

		val = enable ? REG_MASKED_FIELD_ENABLE(FW_BLC_SELF_EN) :

			       REG_MASKED_FIELD_DISABLE(FW_BLC_SELF_EN);

		intel_de_write(display, FW_BLC_SELF, val);

		intel_de_posting_read(display, FW_BLC_SELF);

	} else if (display->platform.i915gm) {
@@ -193,8 +193,8 @@ static bool _intel_set_memory_cxsr(struct intel_display *display, bool enable) 
		 * FW_BLC_SELF. What's going on?

		 */

		was_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;

		val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :

			       _MASKED_BIT_DISABLE(INSTPM_SELF_EN);

		val = enable ? REG_MASKED_FIELD_ENABLE(INSTPM_SELF_EN) :

			       REG_MASKED_FIELD_DISABLE(INSTPM_SELF_EN);

		intel_de_write(display, INSTPM, val);

		intel_de_posting_read(display, INSTPM);

	} else {

drivers/gpu/drm/i915/display/intel_display_irq.c

+2 −2
Original line number Diff line number Diff line
@@ -1619,7 +1619,7 @@ static void i915gm_irq_cstate_wa_enable(struct intel_display *display) 
	 */

	if (display->irq.vblank_enabled++ == 0)

		intel_de_write(display, SCPD0,

			       _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));

			       REG_MASKED_FIELD_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));

}



static void i915gm_irq_cstate_wa_disable(struct intel_display *display)
@@ -1628,7 +1628,7 @@ static void i915gm_irq_cstate_wa_disable(struct intel_display *display) 


	if (--display->irq.vblank_enabled == 0)

		intel_de_write(display, SCPD0,

			       _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));

			       REG_MASKED_FIELD_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));

}



void i915gm_irq_cstate_wa(struct intel_display *display, bool enable)

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

+1 −1
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ void gen6_ppgtt_enable(struct intel_gt *gt) 
	if (HAS_PPGTT(uncore->i915)) /* may be disabled for VT-d */

		intel_uncore_write(uncore,

				   GFX_MODE,

				   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));

				   REG_MASKED_FIELD_ENABLE(GFX_PPGTT_ENABLE));

}



/* PPGTT support for Sandybdrige/Gen6 and later */

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+5 −5
Original line number Diff line number Diff line
@@ -1233,7 +1233,7 @@ static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine) 
	     engine->class == VIDEO_ENHANCEMENT_CLASS ||

	     engine->class == COMPUTE_CLASS ||

	     engine->class == OTHER_CLASS))

		engine->tlb_inv.request = _MASKED_BIT_ENABLE(val);

		engine->tlb_inv.request = REG_MASKED_FIELD_ENABLE(val);

	else

		engine->tlb_inv.request = val;
@@ -1628,7 +1628,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine, 
	const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);

	int err;



	intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));

	intel_uncore_write_fw(uncore, mode, REG_MASKED_FIELD_ENABLE(STOP_RING));



	/*

	 * Wa_22011802037: Prior to doing a reset, ensure CS is
@@ -1636,7 +1636,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine, 
	 */

	if (intel_engine_reset_needs_wa_22011802037(engine->gt))

		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),

				      _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));

				      REG_MASKED_FIELD_ENABLE(GEN12_GFX_PREFETCH_DISABLE));



	err = __intel_wait_for_register_fw(engine->uncore, mode,

					   MODE_IDLE, MODE_IDLE,
@@ -1692,7 +1692,7 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) 
{

	ENGINE_TRACE(engine, "\n");



	ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));

	ENGINE_WRITE_FW(engine, RING_MI_MODE, REG_MASKED_FIELD_DISABLE(STOP_RING));

}



static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
@@ -2552,7 +2552,7 @@ void xehp_enable_ccs_engines(struct intel_engine_cs *engine) 
		return;



	intel_uncore_write(engine->uncore, GEN12_RCU_MODE,

			   _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));

			   REG_MASKED_FIELD_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));

}



#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)

drivers/gpu/drm/i915/gt/intel_engine_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine) 
	if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {

		intel_uncore_write(engine->gt->uncore,

				   RC_PSMI_CTRL_GSCCS,

				   _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));

				   REG_MASKED_FIELD_DISABLE(IDLE_MSG_DISABLE));

		/* hysteresis 0xA=5us as recommended in spec*/

		intel_uncore_write(engine->gt->uncore,

				   PWRCTX_MAXCNT_GSCCS,