Commit dd49ee46 authored by Andy Yan's avatar Andy Yan Committed by Heiko Stuebner
Browse files

drm/rockchip: vop2: Set YUV/RGB overlay mode 



Set overlay mode register according to the
output mode is yuv or rgb.

Signed-off-by: default avatarAndy Yan <andy.yan@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20231211115805.1785073-1-andyshrk@163.com
parent d1f8face

drivers/gpu/drm/rockchip/rockchip_drm_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ struct rockchip_crtc_state { 
	int output_bpc;

	int output_flags;

	bool enable_afbc;

	bool yuv_overlay;

	u32 bus_format;

	u32 bus_flags;

	int color_space;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

+14 −3
Original line number Diff line number Diff line
@@ -1623,6 +1623,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, 


	vop2->enable_count++;



	vcstate->yuv_overlay = is_yuv_output(vcstate->bus_format);



	vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY);



	polflags = 0;
@@ -1650,7 +1652,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, 
	if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode))

		dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP;



	if (is_yuv_output(vcstate->bus_format))

	if (vcstate->yuv_overlay)

		dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y;



	vop2_dither_setup(crtc, &dsp_ctrl);
@@ -1959,10 +1961,12 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) 
	u16 hdisplay;

	u32 bg_dly;

	u32 pre_scan_dly;

	u32 ovl_ctrl;

	int i;

	struct vop2_video_port *vp0 = &vop2->vps[0];

	struct vop2_video_port *vp1 = &vop2->vps[1];

	struct vop2_video_port *vp2 = &vop2->vps[2];

	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);



	adjusted_mode = &vp->crtc.state->adjusted_mode;

	hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
@@ -1975,7 +1979,15 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) 
	pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len;

	vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly);



	vop2_writel(vop2, RK3568_OVL_CTRL, 0);

	ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL);

	ovl_ctrl |= RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD;

	if (vcstate->yuv_overlay)

		ovl_ctrl |= RK3568_OVL_CTRL__YUV_MODE(vp->id);

	else

		ovl_ctrl &= ~RK3568_OVL_CTRL__YUV_MODE(vp->id);



	vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl);



	port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL);

	port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT;
@@ -2049,7 +2061,6 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) 


	vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel);

	vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel);

	vop2_writel(vop2, RK3568_OVL_CTRL, RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD);

}



static void vop2_setup_dly_for_windows(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

+1 −0
Original line number Diff line number Diff line
@@ -401,6 +401,7 @@ enum dst_factor_mode { 
#define VOP2_COLOR_KEY_MASK				BIT(31)



#define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD		BIT(28)

#define RK3568_OVL_CTRL__YUV_MODE(vp)			BIT(vp)



#define RK3568_VP_BG_MIX_CTRL__BG_DLY			GENMASK(31, 24)